User Tools

Site Tools


sessions

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision
Previous revision
sessions [2021/03/25 09:20] – [Schedule of Paper Presentations] yaglikcasessions [2021/05/27 14:22] (current) alserm
Line 23: Line 23:
 ====== Schedule of Paper Presentations ====== ====== Schedule of Paper Presentations ======
 ^ First/Last Name ^ Session (Order in Day) and Date ^ Paper ^ Mentor #1 ^ Mentor #2 ^ Mentor #3 ^  ^ First/Last Name ^ Session (Order in Day) and Date ^ Paper ^ Mentor #1 ^ Mentor #2 ^ Mentor #3 ^
-| Lukas Egeling | S1.1 \\ 25 March |    [[ https://spectreattack.com/spectre.pdf | Spectre Attacks: Exploiting Speculative Execution, IEEE Symposium on Security and Privacy 2019 ]] | Hasan Hassan | Jawad Haj-Yahya | Jeremie Kim | +| Lukas Egeling | S1.1 \\ 25 March |    [[ https://spectreattack.com/spectre.pdf | Spectre Attacks: Exploiting Speculative Execution, IEEE Symposium on Security and Privacy 2019 ]] | Hasan Hassan | Jawad Haj-Yahya | Jeremie Kim | 
-| Sofie Daniels | S1.2 \\ 25 March |    [[ https://arxiv.org/pdf/2102.05981.pdf | BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021 ]] \\ [[ blockhammer-presentation.pptx | [PPT] ]] [[ blockhammer-presentation.pdf | [PDF] ]] | Abdullah Giray Yaglikci | Jeremie Kim | Haocong Luo |+| Sofie Daniels | S1.2 \\ 25 March |    [[ https://arxiv.org/pdf/2102.05981.pdf | BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021 ]] | Abdullah Giray Yaglikci | Jeremie Kim | Haocong Luo |
 | @#CEECF5: Axel Schwarzenbach | @#CEECF5: S2.1 \\ 1 April | @#CEECF5:   [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=388edc&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]] | @#CEECF5: Jeremie Kim | @#CEECF5: Abdullah Giray Yaglikci | @#CEECF5: Hasan Hassan | | @#CEECF5: Axel Schwarzenbach | @#CEECF5: S2.1 \\ 1 April | @#CEECF5:   [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=388edc&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fdrange-dram-latency-based-true-random-number-generator_hpca19.pdf | D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. ]] | @#CEECF5: Jeremie Kim | @#CEECF5: Abdullah Giray Yaglikci | @#CEECF5: Hasan Hassan |
 | @#CEECF5: Lorenzo Rai | @#CEECF5: S2.2 \\ 1 April | @#CEECF5:    [[ https://parallel.princeton.edu/papers/micro19-gao.pdf | ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]] | @#CEECF5: Geraldo Francisco De Oliveira Junior | @#CEECF5: Nastaran Hajinazar | @#CEECF5: João Dinis Ferreira | | @#CEECF5: Lorenzo Rai | @#CEECF5: S2.2 \\ 1 April | @#CEECF5:    [[ https://parallel.princeton.edu/papers/micro19-gao.pdf | ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 ]] | @#CEECF5: Geraldo Francisco De Oliveira Junior | @#CEECF5: Nastaran Hajinazar | @#CEECF5: João Dinis Ferreira |
 | Georg Streich | S3.1 \\ 15 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=476ab4&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA, 2015. ]] | Juan Gomez Luna | Rahul Bera | Geraldo Francisco De Oliveira Junior | | Georg Streich | S3.1 \\ 15 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=476ab4&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fpim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA, 2015. ]] | Juan Gomez Luna | Rahul Bera | Geraldo Francisco De Oliveira Junior |
-| Alfio Di Mauro | S3.2 \\ 15 April |    [[ https://people.inf.ethz.ch/omutlu/pub/FIGARO-fine-grained-in-DRAM-data-relocation-and-caching_micro20.pdf | FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, MICRO 2020 ]] | Lois Orosa Nogueira | Konstantinos Kanellopoulos | Haocong Luo | 
 | @#CEECF5: Bastian Amrhein | @#CEECF5: S4.1 \\ 22 April | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=b927d2&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks, ISCA 2009. ]] | @#CEECF5: Minesh Hamenbhai Patel | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Haiyu Mao | | @#CEECF5: Bastian Amrhein | @#CEECF5: S4.1 \\ 22 April | @#CEECF5: [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?tok=b927d2&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Fbless_isca09.pdf | A Case for Bufferless Routing in On-Chip Networks, ISCA 2009. ]] | @#CEECF5: Minesh Hamenbhai Patel | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Haiyu Mao |
-|  @#CEECF5: Paul Scheffler |  @#CEECF5: S4.2 \\ 22 April |  @#CEECF5:    [[ http://tnm.engin.umich.edu/wp-content/uploads/sites/353/2021/01/2021.02.Prodigy_HPCA2021_Camera_Ready.pdf | Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021 ]] |  @#CEECF5: Rahul Bera |  @#CEECF5: Konstantinos Kanellopoulos |  @#CEECF5: Juan Gomez-Luna |+| @#CEECF5:​ Paul Scheffler | @#CEECF5: S4.2 \\ 22 April | @#CEECF5:  ​ [[ http://tnm.engin.umich.edu/wp-content/uploads/sites/353/2021/01/2021.02.Prodigy_HPCA2021_Camera_Ready.pdf | Prodigy:​ Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021 ]] | @#CEECF5:​ Rahul Bera | @#CEECF5:​ Konstantinos Kanellopoulos | @#CEECF5: Juan Gomez-Luna |
 | Nils Wistoff | S5.1 \\ 29 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?media=perceptron_branch_predictor.pdf | Dynamic branch prediction with perceptrons, HPCA 2001. ]] | Can Firtina | Hasan Hassan | Behzad Salami | | Nils Wistoff | S5.1 \\ 29 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?media=perceptron_branch_predictor.pdf | Dynamic branch prediction with perceptrons, HPCA 2001. ]] | Can Firtina | Hasan Hassan | Behzad Salami |
 | Valery Fischer | S5.2 \\ 29 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=5d56bf&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Frlmc_isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008. ]] | Gagandeep Singh | Jisung Park | Can Firtina | | Valery Fischer | S5.2 \\ 29 April |    [[ https://safari.ethz.ch/architecture_seminar/spring2019/lib/exe/fetch.php?tok=5d56bf&media=https%3A%2F%2Fpeople.inf.ethz.ch%2Fomutlu%2Fpub%2Frlmc_isca08.pdf | Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008. ]] | Gagandeep Singh | Jisung Park | Can Firtina |
Line 38: Line 37:
 | Bernard Pranjic | S7.2 \\ 20 May |   [[ http://cccp.eecs.umich.edu/papers/shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]] | Behzad Salami | Kosta Stojiljkovic | Damla Senol Cali | | Bernard Pranjic | S7.2 \\ 20 May |   [[ http://cccp.eecs.umich.edu/papers/shrupad-micro17.pdf | Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 ]] | Behzad Salami | Kosta Stojiljkovic | Damla Senol Cali |
 | @#CEECF5: Benjamin Gundersen | @#CEECF5: S8.1 \\ 27 May | @#CEECF5:   [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]] | @#CEECF5: Konstantinos Kanellopoulos | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Gagandeep Singh | | @#CEECF5: Benjamin Gundersen | @#CEECF5: S8.1 \\ 27 May | @#CEECF5:   [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=10.1.1.20.8558.pdf | Multiscalar Processors, ISCA 1995. ]] | @#CEECF5: Konstantinos Kanellopoulos | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Gagandeep Singh |
-| @#CEECF5: Andrea Lepori | @#CEECF5: S8.\\ 27 May | @#CEECF5:    [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=p294-rajwar.pdf | Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001. ]] | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Minesh Hamenbhai Patel | @#CEECF5: Kosta Stojiljkovic |+| @#CEECF5: Andrea Lepori | @#CEECF5: S8.\\ 27 May | @#CEECF5:    [[ https://safari.ethz.ch/architecture_seminar/fall2018/lib/exe/fetch.php?media=p294-rajwar.pdf | Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001. ]] | @#CEECF5: Nika Mansouri Ghiasi | @#CEECF5: Minesh Hamenbhai Patel | @#CEECF5: Kosta Stojiljkovic
 +| Alfio Di Mauro | S9.1 \\ 3 June |    [[ https://people.inf.ethz.ch/omutlu/pub/FIGARO-fine-grained-in-DRAM-data-relocation-and-caching_micro20.pdf | FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, MICRO 2020 ]] | Lois Orosa Nogueira | Konstantinos Kanellopoulos | Haocong Luo |
sessions.1616664051.txt.gz · Last modified: 2021/03/25 09:20 by yaglikca