User Tools

Site Tools


This is an old revision of the document!

Presentation Preparation and Sessions

Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper.

Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).

Please use the following algorithm to prepare for your talk:

  • Step 2: Check your assigned paper and presentation date.
  • Step 3: Contact your Mentor #1, Mentor #2, and Mentor #3 (if applicable) to schedule a meeting (do it now).
  • Step 4: Read and analyze your paper thoroughly.
  • Step 5: Discuss with anyone you wish + use any resources.
  • Step 6: Prepare a draft presentation based on guidelines (Study Lecture 1 and 2 again for presentation guidelines).
  • Step 7: Meet mentors and get feedback. Meetings are mandatory – you have to schedule them with your assigned mentors.
  • Step 8: Revise the presentation and delivery.
  • Step 9: Meet mentors again and get further feedback.
  • Step 10: Revise the presentation and delivery.
  • Step 11: Practice, practice, practice.

We look forward to you participating in an enjoyable seminar course this semester.

Schedule of Paper Presentations

Last Name First Name Paper Mentor #1 Mentor #2 Mentor #3 Session (Order in Day) and Date
Schoellen Felix Architecture of the IBM System/360, IBM Journal of Research and Development 1964. Geraldo Francisco De Oliveira Junior Damla Senol Cali S1.1
15 Oct
Becker Olivier Aergia: Exploiting Packet Latency Slack in On-Chip Networks, ISCA, 2010 Nika Mansouri Ghiasi Kosta Stojiljkovic S1.2
15 Oct
Vilums Georgijs MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP, MICRO 2012. Jawad Haj-Yahya Kosta Stojiljkovic S2.1
22 Oct
Maisch Leandra Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads, MICRO 2016 Minesh Hamenbhai Patel Haiyu Mao S2.2
Weidmann Theo Flexible Reference Counting-Based Hardware Acceleration for Garbage Collection, ISCA 2009 Geraldo Francisco De Oliveira Junior Konstantinos Kanellopoulos S3.1
29 Oct
Scholbe Stefan The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework, ISCA, 2020 Lois Orosa Nogueira Jisung Park Nastaran S3.2
29 Oct
Bjelajac Stefan Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks, ASPLOS 2018. Damla Senol Cali Juan Gomez Luna S4.1
5 Nov
Adatte Quentin A Logic-in-Memory Computer, IEEE Trans. Comput., 1970 Gagandeep Singh Nika Mansouri Ghiasi S4.2
5 Nov
Brechbühl Jérome Using Memory Errors to Attack a Virtual Machine, IEEE Symposium on Security and Privacy, 2003 Minesh Hamenbhai Patel Rahul Bera S5.1
12 Nov
Müller Julian TRRespass: Exploiting the Many Sides of Target Row Refresh, IEEE Symposium on Security and Privacy, 2020 Abdullah Giray Yaglikci Hasan Hassan S5.2
12 Nov
Schumacher David D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. Jeremie Kim Mohammed Alser S6.1
19 Nov
Meier Christopher ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 Juan Gomez Luna Nastaran S6.2
19 Nov
Loher Timo Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks, ISCA 2018. Jisung Park João Dinis Ferreira S7.1
26 Nov
Kleymann David Online Design Bug Detection: RTL Analysis, Flexible Mechanisms, and Evaluation, MICRO, 2008 Rahul Bera Haiyu Mao Jeremie Kim S7.2
26 Nov
Esterhammer Arno RAMBleed: Reading Bits in Memory Without Accessing Them, IEEE Symposium on Security and Privacy, 2020. Hasan Hassan Abdullah Giray Yaglikci S8.1
3 Dec
Krattenmacher Jascha A2: Analog malicious hardware, IEEE Symposium on Security and Privacy, 2016. Lois Orosa Nogueira Jawad Haj-Yahya S8.2
3 Dec
Oberdörfer Tobias Shouji: A Fast and Efficient Pre-Alignment Filter for Sequence Alignment, Bioinformatics 2019 Mohammed Alser Can Firtina S9.1
10 Dec
Xuan Cheng Hardware-Software Co-Design for Brain-Computer Interfaces, ISCA, 2020 Konstantinos Kanellopoulos Gagandeep Singh S9.2
10 Dec
Vitez Victor A programmable chemical computer with memory and pattern recognition, Nature Communications, 2020 Can Firtina João Dinis Ferreira S10.1
17 Dec
17 Dec
sessions.1601560180.txt.gz · Last modified: 2021/02/05 09:35 (external edit)