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Presentation Preparation and Sessions

Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper.

Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).

Please use the following algorithm to prepare for your talk:

  • Step 2: Check your assigned paper and presentation date.
  • Step 3: Contact your Mentor #1, Mentor #2, and Mentor #3 to schedule a meeting (do it now).
  • Step 4: Read and analyze your paper thoroughly.
  • Step 5: Discuss with anyone you wish + use any resources.
  • Step 6: Prepare a draft presentation based on guidelines (Study Lecture 1 and 2 again for presentation guidelines).
  • Step 7: Meet mentors and get feedback. Meetings are mandatory – you have to schedule them with your assigned mentors.
  • Step 8: Revise the presentation and delivery.
  • Step 9: Meet mentors again and get further feedback.
  • Step 10: Revise the presentation and delivery.
  • Step 11: Practice, practice, practice.

We look forward to you participating in an enjoyable seminar course this semester.

Schedule of Paper Presentations

First/Last Name Session (Order in Day) and Date Paper Mentor #1 Mentor #2 Mentor #3
Lukas Egeling S1.1
25 March
Spectre Attacks: Exploiting Speculative Execution, IEEE Symposium on Security and Privacy 2019 Hasan Hassan Jawad Haj-Yahya Jeremie Kim
Sofie Daniels S1.2
25 March
BlockHammer: Preventing RowHammer at Low Cost by Blacklisting Rapidly-Accessed DRAM Rows, HPCA 2021 Abdullah Giray Yaglikci Jeremie Kim Haocong Luo
Axel Schwarzenbach S2.1
1 April
D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput, HPCA 2019. Jeremie Kim Abdullah Giray Yaglikci Hasan Hassan
Lorenzo Rai S2.2
1 April
ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs, MICRO 2019 Geraldo Francisco De Oliveira Junior Nastaran Hajinazar João Dinis Ferreira
Georg Streich S3.1
15 April
PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture, ISCA, 2015. Juan Gomez Luna Rahul Bera Geraldo Francisco De Oliveira Junior
Alfio Di Mauro S3.2
15 April
FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching, MICRO 2020 Lois Orosa Nogueira Konstantinos Kanellopoulos Haocong Luo
Bastian Amrhein S4.1
22 April
A Case for Bufferless Routing in On-Chip Networks, ISCA 2009. Minesh Hamenbhai Patel Nika Mansouri Ghiasi Haiyu Mao
Paul Scheffler S4.2
22 April
Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design, HPCA 2021 Rahul Bera Konstantinos Kanellopoulos Juan Gomez-Luna
Nils Wistoff S5.1
29 April
Dynamic branch prediction with perceptrons, HPCA 2001. Can Firtina Hasan Hassan Behzad Salami
Valery Fischer S5.2
29 April
Self Optimizing Memory Controllers: A Reinforcement Learning Approach, ISCA 2008. Gagandeep Singh Jisung Park Can Firtina
Hong Chul Nam S6.1
6 May
Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding, ArXiv 2016. Haiyu Mao Lois Orosa Nogueira Jisung Park
Robert Veres S6.2
6 May
SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs, Bioinformatics 2020 Mohammed Alser Can Firtina Damla Senol Cali
Francois Costa S7.1
20 May
The Alpha 21264 Microprocessor, IEEE Micro 1999 Jisung Park Rahul Bera Jawad Haj-Yahya
Bernard Pranjic S7.2
20 May
Mirage cores: the illusion of many out-of-order cores using in-order hardware, MICRO 2017 Behzad Salami Kosta Stojiljkovic Damla Senol Cali
Benjamin Gundersen S8.1
27 May
Multiscalar Processors, ISCA 1995. Konstantinos Kanellopoulos Nika Mansouri Ghiasi Gagandeep Singh
Andrea Lepori S8.1
27 May
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution, MICRO 2001. Nika Mansouri Ghiasi Minesh Hamenbhai Patel Kosta Stojiljkovic
sessions.1615404106.txt.gz · Last modified: 2021/03/10 20:21 by alserm