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Presentation Preparation and Sessions

Please check the paper assignment below and remember the presentation date. Please start preparing to present your assigned paper.

Each student will present and analyze one paper (maximum 30 minutes) and lead discussion+brainstorming+feedback (maximum 20 minutes).

Please use the following algorithm to prepare for your talk:

  • Step 2: Check your assigned paper and presentation date.
  • Step 3: Contact your Mentor #1, Mentor #2, and Mentor #3 to schedule a meeting (do it now). You need to meet mentors at least twice before you can present in class.
  • Step 4: Read and analyze your paper thoroughly.
  • Step 5: Discuss with anyone you wish + use any resources.
  • Step 6: Prepare a draft presentation based on guidelines (Study Lecture 1 and 2 again for presentation guidelines).
  • Step 7: Meet mentors and get feedback. Meetings are mandatory – you have to schedule them with your assigned mentors.
  • Step 8: Revise the presentation and delivery.
  • Step 9: Meet mentors again and get further feedback.
  • Step 10: Revise the presentation and delivery.
  • Step 11: Practice, practice, practice.

We look forward to you participating in an enjoyable seminar course this semester.

Schedule of Paper Presentations

Student Name Session number and Date Mentor 1 Mentor 2 Mentor 3 Assigned paper
Shashank
Anand
S1.1
7.4
Geraldo De Oliveira Junior Nika Mansouri João Dinis Sanches Ferreira A Logic-in-Memory Computer", IEEE Trans. Comput., 1970
Yanick
Schimpf
S1.2
7.4
Juan Gomez Luna Konstantinos Kanellopoulos Mohammad Sadrosadati SISA: Set-Centric Instruction Set Architecture for Graph Mining on Processing-in-Memory Systems, MICRO 2021
Naoise
Tobin
S2.1
14.4
Haocong Luo Giray Yaglikci Hasan Hassan Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors, ISCA 2014.
Aleksandar
Terzic
S2.2
14.4
Hasan Hassan Ataberk Olgun Giray Yaglikci Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications, MICRO 2021
Gianluca
Figini
S3.1
28.4
Can Firtina Mohammed Alser Joel Lindegger ProSE: The Architecture and Design of a Protein Discovery Engine, ASPLOS 2022
Jennifer
Schmitz
S3.2
28.4
Nika Mansouri Jisung Park Mohammed Alser GenStore: a high-performance in-storage processing system for genome sequence analysis, ASPLOS 2022
Jan
Mantsch
S4.1
5.5
Jisung Park Mohammad Sadrosadati Rahul Bera Focusing processor policies via critical-path prediction, ISCA 2001
Cedric
Caspar
S4.2
5.5
Rahul Bera Konstantinos Kanellopoulos Rakesh Nadig Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning, MICRO 2021
Jakub
Mandula
S5.1
12.5
Gagandeep Singh Joel Lindegger Nika Mansouri Ten Lessons From Three Generations Shaped Google's TPUv4i, ISCA 2021
Lotte
Seifert
S5.2
12.5
Geraldo De Oliveira Junior Rahul Bera Gagandeep Singh Google Neural Network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks, PACT 2021
Nicolas
Winkler
S6.1
19.5
Konstantinos Kanellopoulos João Dinis Sanches Ferreira Rakesh Nadig Hash, Don't Cache (the Page Table), SIGMETRICS 2016
Andrew
Dobis
S6.2
19.5
Mohammad Sadrosadati Haocong Luo Geraldo De Oliveira Junior Processing-In-Memory Enabled Graphics Processors for 3D Rendering, HPCA 2017
Maria
Makeenkova
S7.1
2.6
Ataberk Olgun Hasan Hassan Konstantinos Kanellopoulos QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips, ISCA 2021
Quirin
Bitter
S7.2
2.6
Giray Yaglikci Haocong Luo Jisung Park A Deeper Look into RowHammer's Sensitivities: Experimental Analysis of Real DRAM Chips and Implications on Future Attacks and Defenses, MICRO 2021
Patrick
Muntwiler
S7.3
2.6
João Dinis Sanches Ferreira Can Firtina Ataberk Olgun A2: Analog malicious hardware, IEEE Symposium on Security and Privacy, 2016.
sessions.txt · Last modified: 2022/05/19 14:21 by alserm