Onur Mutlu and Co-authors Receive the 2021 HPCA Test of Time Award

Congratulations to Onur Mutlu and co-authors on receiving the HPCA Test of Time Award for their 2003 HPCA paper:

Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors
Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt

The IEEE International Symposium on High-Performance Computer Architecture (HPCA) Test of Time Award recognizes the most influential papers published in prior sessions of HPCA (held 18-22 years ago), and that have had a significant impact in the field.

The paper was Professor Onur Mutlu’s first publication during his PhD at the University of Texas with his PhD advisor Professor Yale Patt and colleagues from Intel, and Dr. Jared Stark and Chris Wilkerson.  The significance of the paper was described by the award committee as: “Runahead Execution is a pioneering paper that opened up new avenues in dynamic prefetching. The basic idea of run ahead execution effectively increases the instruction window very significantly, without having to increase physical resource size (e.g. the issue queue). This seminal paper spawned off a new area of ILP-enhancing microarchitecture research. This work has had strong industry impact as evidenced by IBM’s POWER6 – Load Lookahead, NVIDIA Denver, and Sun ROCK’s hardware scouting.” The award was presented last week at HPCA 2021 on March 2, 2021.

Watch Onur’s Retrospective HPCA Test of Time Award Talk Video (14 minutes)


Onur Mutlu
, Jared Stark, Chris Wilkerson, and Yale N. Patt,
“Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors”
Proceedings of the 9th International Symposium on High-Performance Computer Architecture (HPCA), pages 129-140, Anaheim, CA, February 2003.
[Talk Slides (pdf)]
[Lecture Slides (pptx) (pdf)]
[Lecture Video (1 hr 54 mins)]
[Retrospective HPCA Test of Time Award Talk Slides (pptx) (pdf)]
[Retrospective HPCA Test of Time Award Talk Video (14 minutes)]
One of the 15 computer architecture papers of 2003 selected as Top Picks by IEEE Micro.
HPCA Test of Time Award (awarded in 2021).

TRRespass wins the Pwnie Award for Most Innovative Research

TRRespass won the Pwnie Award for “Most Innovative Research” at the annual BlackHat Europe conference this week.  Pwnies are the most prestigious industrial awards in the security community.   Congratulations to the authors: Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi on this prestigious prize!

We recently interviewed Hasan Hassan about his contribution to TRRespass.  Here’s what he had to say:

You were a co-author on TRRespass, which recently won a Best Paper Award at IEEE S&P. What is the significance of this paper?

Shortly after the discovery of the RowHammer vulnerability of DRAM, DRAM vendors announced RowHammer-free DRAM devices that implement in-DRAM solutions to protect against RowHammer. However, in TRRespass, we find that such solutions, commonly referred to as Target Row Refresh (TRR), do not effectively protect against RowHammer attacks when many rows are hammered at the same time. We show that the RowHammer vulnerability is not only still intact on the current DDR4 devices, but it has also become worse due to technology node scaling.

How was your experience in collaborating with the Systems and Network Security Group at VU Amsterdam on this work?

I am glad that our combined effort with the Systems and Network Security Group at VU Amsterdam won us the Best Paper Award at IEEE S&P. It has been a great experience for me to collaborate with experts in hardware security. I hope there will be more such collaborations that result in impactful research.

Which tools did you use in this work?

I think SoftMC, our FPGA-based DRAM testing infrastructure, was one of the key enablers of this research. We used SoftMC to interface with DDR4 DRAM chips in a much more flexible way than anyone can do using commodity desktop and mobile systems. Specifically, we used SoftMC to communicate with DRAM chips using low-level DDR4 commands as opposed to using load/store instructions provided by typical instruction set architectures. In a way, SoftMC lets us be the memory controller and provides the flexibility of issuing any DDR4 command at any time, which is not possible with commodity systems.

An earlier version of SoftMC that supports DDR3 devices is open-source and can be accessed here. In 2017, we published a paper that describes the design of SoftMC in detail.

I am also involved in maintaining Ramulator, a cycle-accurate DRAM simulator that we describe in this paper, and Scarab, which is a cycle-accurate simulator for state-of-the-art multicore CPUs.


Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”Proceedings of the 41st IEEE Symposium on Security and Privacy (S&P), San Francisco, CA, USA, May 2020.
Slides (pptx) (pdf)
Lecture Slides (pptx) (pdf)
Talk Video (17 minutes)
Lecture Video (59 minutes)
Source Code
Web Article
Project Overview
Best paper award.
Pwnie Award 2020 for Most Innovative Research. Pwnie Awards 2020

Award: Jisung Park was awarded a Postdoctoral Research Fellowship

Jisung Park was awarded a Postdoctoral Research Fellowship from the National Research Foundation of Korea for his project on “Storage System Design for Machine Learning Applications”.

Congratulations Jisung — We look forward to having you in the group for another year!

The NRF Postdoctoral Research Fellowship supports promising Korean postdoctoral researchers in all fields of science and engineering for one year.

 

 

Papers: We are at ISCA 2020 this week (virtually)!

We are attending ISCA 2020 this week, 29 May – 3 June, online: https://iscaconf.org/isca2020/.

Congratulations to Nastaran Hajinazar on winning the photo contest!

We are excited to be presenting several papers this year — join us for our talks, or watch the recordings any time:

Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu,
“Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (20 minutes)]


Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Yaglikci, Lois Orosa, Jisung Park, and Onur Mutlu,
“CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (20 minutes)]


Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, and Onur Mutlu,
“The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (26 minutes)]


Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A. Giray Yaglikci, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu,
“SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]

Award: TRRespass wins the Best Paper Award at IEEE S&P!

Our recent paper “TRRespass: Exploiting the Many Sides of Target Row Refresh”, in collaboration with the Systems and Network Security Group at VU Amsterdam has been awarded the Best Paper Award at the 41st IEEE Symposium on Security and Privacy!

Congratulations to the authors: Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi

Rowhammer, the DRAM vulnerability that was supposedly fixed in DDR4 is not fixed in DDR4. The TRRespass attack shows that DIMMs from all 3 major vendors (good for 95% of the market) are still vulnerable.

Read the news story: NakedSecurity
Paper: “TRRespass: Exploiting the Many Sides of Target Row Refresh”
Talk Video
Source Code
Project Overview

 

 

Best Paper Award at DSN 2019!

Congratulations to Minesh Patel, Jeremie Kim, Hasan Hassan, and Onur Mutlu for the Best Paper Award at this year’s IEEE/IFIP International Conference on Dependable Systems and Networks (DSN)!

The DSN Best Paper Award recognises the best accepted scientific paper among all papers from the conference.  DSN is the top conference in fault tolerant and dependable computing, so this is a great achievement, congratulations!

The Talk video and slides for our award paper “Understanding and Modeling On-Die Error Correction in Modern DRAM: An Experimental Study Using Real Devices” are now available:

Paper (PDF)
Slides (pptx) (pdf)
Video: (youtube