readings
Table of Contents
Readings
Books
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- D. Harris and S. Harris, "Digital Design and Computer Architecture (1st Edition)." H&H textbooks are available online (through the ETH network or the ETH VPN).
Lecture 1 (22.02 Thu.)
Suggested readings (Lecture 1):
- Digital Design and Computer Architecture, David Harris and Sarah Harris, ISBN-10: 0123704979
Mentioned in Lecture 1:
Lecture 20 (10.05 Fri.)
Reading assignments (Lecture 20):
- Smith and Sohi, “The Microarchitecture of Superscalar Processors,” Proceedings of the IEEE, 1995
- D. Harris and S. Harris, “Chapter 7.8 - 7.9”
Suggested readings in Lecture 20:
- Tomasulo, “An Efficient Algorithm for Exploiting Multiple Arithmetic Units,” IBM Journal of R&D, Jan. 1967.
- Smith and Plezskun, “Implementing Precise Interrupts in Pipelined Processors,” IEEE Trans on Computers 1988 and ISCA 1985.
- Hwu and Patt, “Checkpoint Repair for Out-of-order Execution Machines,” ISCA 1987.
Mentioned in Lecture in Lecture 20:
- Smith and Sohi, “The Microarchitecture of Superscalar Processors,” Proc. IEEE, Dec. 1995.
- Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro, March-April 1999.
- Yeager, “The MIPS R10000 Superscalar Microprocessor,” IEEE Micro, April 1996
- Tendler et al.,“POWER4 system microarchitecture,” IBM J R&D, 2002.
- Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004.
- Patt, Hwu, Shebanow, “HPS, a new microarchitecture: rationale and introduction,” MICRO 1985.
- Patt et al., “Critical issues regarding HPS, a high performance microarchitecture,” MICRO 1985.
Lecture 21 (16.05 Thu.)
Reading assignments (Lecture 21):
- Lindholm et al., “NVIDIA Tesla: A Unified Graphics and Computing Architecture,” IEEE Micro 2008
Suggested in Lecture 21:
- Peleg and Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro 1996
Mentioned in Lecture 21:
- Patt, “Requirements, bottlenecks, and good fortune: agents for microprocessor evolution,”, Proc. of the IEEE 2001
- Mike Flynn, “Very High-Speed Computing Systems,” Proc. of IEEE, 1966
- Gene M. Amdahl, “Validity of the single processor approach to achieving large scale computing capabilities,” AFIPS Conference, April 1967
- Butler W. Lampson, “Hints for Computer System Design,” ACM Operating Systems Review, 1983
- Fisher, “Very Long Instruction Word architectures and the ELI-512,” ISCA 1983.
- Russell, “The CRAY-1 Computer System,” CACM 1978.
- Cray Research Inc., “The CRAY X-MP Series of Computer Systems,” 1985
- Rau, “Pseudo-Randomly Interleaved Memory,” ISCA 1991
- E. Lindholm, J. Nickolls, S. Oberman, J. Montrym, “NVIDIA Tesla: A Unified Graphics and Computing Architecture,” IEEE Micro, 2008
- Fung et al., “Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow,” MICRO 2007
- NVIDIA, “NVIDIA GeForce GTX 200 GPU. Architectural Overview. White Paper,” 2008
- NVIDIA, “NVIDIA Tesla V100 GPU Architecture. White Paper,” 2017
- M. A. Raihan, N. Goli and T. M. Aamodt, “Modeling Deep Learning Accelerator Enabled GPUs,” ISPASS 2019
- Narasiman et al., “Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,” MICRO 2011
Lecture 24 (24.05 Fri.)
Reading assignments (Lecture 24):
- D. Harris and S. Harris, “H&H Chapters 8.1 - 8.3”
- Y.N. Patt and S.J. Patel, “Refresh: P&P Chapter 3.5”
Suggested readings (Lecture 24):
Mentioned in Lecture 24:
readings.txt · Last modified: 2024/05/24 12:33 by kanellok