labs
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* The deadline for each lab is the next lab session. At the beginning of the next lab session, you should ask a TA to review your lab. For instance, if your group is Tuesday, the deadline for Lab 1 is Tuesday, 13.03. | * The deadline for each lab is the next lab session. At the beginning of the next lab session, you should ask a TA to review your lab. For instance, if your group is Tuesday, the deadline for Lab 1 is Tuesday, 13.03. | ||
- | ^ Lab ^ Tuesday ^ Wednesday ^ Friday (2 sessions) ^ Manual ^ | + | ^ Lab ^ Tuesday ^ Wednesday ^ Friday (2 sessions) ^ Manual, Report and Files ^ Slides |
- | | Lab 1: Drawing a Basic Circuit |06.03 |07.03 |09.03| {{Lab1.pdf|Lab1 Manual}} | + | | Lab 1: Drawing a Basic Circuit |06.03 |07.03 |09.03| {{Lab1.pdf|Lab1 Manual}}| {{digitaldesign-s18-lab1_supplement_beforelab.pdf|Lab1 Supplement |
- | | Lab 2: Mapping Your Circuit to FPGA |13.03 |14.03 |16.03| {{Lab2.pdf|Lab2 Manual}} | | + | | Lab 2: Mapping Your Circuit to FPGA |13.03 |14.03 |16.03| {{Lab2.pdf|Lab2 Manual}} |
- | | Lab 3: Verilog for Combinatorial Circuits |20.03 |21.03 |23.03| {{Lab3.pdf|Lab3 Manual}} | | + | | Lab 3: Verilog for Combinatorial Circuits |20.03 |21.03 |23.03| {{Lab3.pdf|Lab3 Manual}} |
- | | Lab 4: Finite State Machines |27.03 |28.03 |13.04| | + | | Lab 4: Finite State Machines |27.03 |28.03 |13.04| |
- | | Lab 5: Implementing an ALU |10.04 |11.04 |20.04| | + | | Lab 5: Implementing an ALU |10.04 |11.04 |20.04| |
- | | Lab 6: Testing the ALU |17.04 |18.04 |27.04| | + | | Lab 6: Testing the ALU |17.04 |18.04 |27.04| |
- | | Lab 7: Writing Assembly Code |24.04 |25.04 |04.05| | + | | Lab 7: Writing Assembly Code |24.04 |25.04 |04.05| |
- | | Lab 8: Full System Integration (Part I) |08.05 |02.05 |11.05| | + | | Lab 8: Full System Integration (Part I) |08.05 |02.05 |11.05|{{Lab8.pdf|Lab8 Manual}} \\ {{Lab8-session1_Report.pdf|Lab8 Session I Report (PDF)}} \\ {{Lab8-session1_Report.doc|Lab8 Session I Report (DOC)}} \\ {{lab8_student_vivado.zip|Lab8 Files}} | {{digitaldesign-s18-lab8_supplement_beforelab.pdf|Lab8 Supplement (PDF)}} \\ {{digitaldesign-s18-lab8_supplement_beforelab.pptx|Lab8 Supplement (PPT)}} |
- | | Lab 8: Full System Integration (Part II) |15.05 |09.05 |18.05| | + | | Lab 8: Full System Integration (Part II) |15.05 |09.05 |18.05| |
- | | Lab 9: The Performance of MIPS |22.05 |16.05 |25.05| | + | | Lab 9: The Performance of MIPS |22.05 |16.05 |25.05|{{Lab9.pdf|Lab9 Manual}} \\ {{Lab9_Report.pdf|Lab9 Report (PDF)}} \\ {{Lab9_Report.doc|Lab9 Report (DOC)}} \\ {{lab9_student.zip|Lab9 Files}} \\ {{lab9_helpers.zip|Lab9 Helper Files}} | {{digitaldesign-s18-lab9_supplement_beforelab.pdf|Lab9 Supplement (PDF)}} \\ {{digitaldesign-s18-lab9_supplement_beforelab.pptx|Lab9 Supplement (PPT)}} |
+ | | Extra Session |29.05 |23.05 |01.06| | ||
===== Working with the FPGA Board ===== | ===== Working with the FPGA Board ===== |
labs.1521542599.txt.gz · Last modified: 2019/02/12 16:34 (external edit)