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Lab Schedule

  • You will work in groups of two. There are 9 labs in total.
  • You will do hands-on exercises and be required to demonstrate your implementation.
  • The required demonstration is mentioned in the lab exercises sheet at the end of the manual. Only the demonstration is required, you do not need to hand in the sheet.
  • The deadline for each lab (in-class evaluation) is the next lab session. At the beginning of the next lab session, you should ask a TA to review your lab. For instance, if your group is Tuesday, the deadline for Lab 1 is Tuesday, 12.03.
  • The deadline for each lab report is in the following table.
Lab Tuesday Wednesday Friday (2 sessions) Manual, Report and Files Slides Deadline (Lab Report)
Lab 1: Drawing a Basic Circuit 05.03 06.03 08.03 Lab1 Manual
Lab1 Report (PDF)
Lab1 Report (DOC)
Lab1 Supplement (PDF)
Lab1 Supplement (PPT)
22.03
Lab 2: Mapping Your Circuit to FPGA 12.03 13.03 15.03 Lab2 Manual
Lab2 Report (PDF)
Lab2 Report (DOC)
Lab2 Supplement (PDF)
Lab2 Supplement (PPT)
29.03
Lab 3: Verilog for Combinatorial Circuits 19.03 20.03 22.03 Lab3 Manual
Lab3 Report (PDF)
Lab3 Report (DOC)
Lab3 Supplement (PDF)
Lab3 Supplement (PPT)
05.04
Lab 4: Finite State Machines 26.03 27.03 29.03 Lab4 Manual
Lab4 Report (PDF)
Lab4 Report (DOC)
Lab4 Supplement (PDF)
Lab4 Supplement (PPT)
12.03
Lab 5: Implementing an ALU 02.04 03.04 05.04 Lab5 Manual
Lab5 Report (PDF)
Lab5 Report (DOC)
Lab5 Supplement (PDF)
Lab5 Supplement (PPT)
19.04
Lab 6: Testing the ALU 09.04 10.04 12.04Lab6 Manual
Lab6 Files
Lab6 Report (PDF)
Lab6 Report (DOC)
Lab6 Supplement (PDF)
Lab6 Supplement (PPT)
26.04
Lab 7: Writing Assembly Code 16.04 17.04 03.05 Lab7 Manual
Lab7 Files
Lab7 Report (PDF)
Lab7 Report (DOC)
Lab7 Supplement (PDF)
Lab7 Supplement (PPT)
17.05
Lab 8: Full System Integration (Part I) 30.04 08.05 10.05Lab8 Manual
Lab8 Files
Lab8.1 Report (PDF)
Lab8.1 Report (DOC)
Lab8 Supplement (PDF)
Lab8 Supplement (PPT)
24.05
Lab 8: Full System Integration (Part II) 07.05 15.05 17.05 Lab8.2 Report (PDF)
Lab8.2 Report (DOC)
Lab8.2 Supplement (PDF)
Lab8.2 Supplement (PPT)
31.05
Lab 9: The Performance of MIPS 14.05 22.05 24.05 Lab9 Manual (pdf)
Lab9 Report (PDF)
Lab9 Report (DOC)
Lab9 Helpers
Lab9 Student
Lab9 Supplement (PDF)
Lab9 Supplement (PPT)
07.06
Extra Session 21.05 29.05 31.05

Working with the FPGA Board

For this course, we use the software Vivado for FPGA programming. The computers in the lab rooms are already installed with the necessary software. If you wish to use your own computer, you can refer to the following instructions: https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-getting-started/start

You can also find examples for the Basys 3 board and a master constraint file here: https://reference.digilentinc.com/reference/programmable-logic/basys-3/start

Help

For technical questions, please write to digitaltechnik@lists.inf.ethz.ch. All lecturers and assistants will receive this e-mail and try to respond quickly. For other inquiries please email the TA or the lecturers.

Frequently Asked Questions:

Q: Can I use my lab grades from previous years?
A: Yes. You can find your past lab grades in Moodle (Spring 2018).

Q: Can I use my lab grades from previous years and still do the labs?
A: Sure! Choose this option on the sign-up form that we provide in Moodle.

Q: Can I do the labs and decide at the end of the semester whether to use my grades from previous years?
A: No. You need to decide at the beginning of the semester (until 01.03.2019 at 23:59).

Q: I don't have a partner. What do I do?
A: Make new friends and find one:) Otherwise we will pair you with another person who has not found a partner.

Q: Can we have groups of three students?
A: No. We will pair you with another person who has not found a partner. Groups of two are much better for your learning experience instead of three so we will only make exceptions if absolutely necessary.

labs.txt · Last modified: 2019/05/14 14:13 (external edit)