labs
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labs [2021/04/12 18:10] – [Lab Schedule] mpatel | labs [2021/05/10 10:30] – mnika | ||
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| Lab 3: Verilog for Combinatorial Circuits |23.03 |24.03 |26.03| {{Lab3_manual.pdf|Lab3 Manual}} \\ {{Lab3_report.pdf|Lab3 Report (PDF)}} \\ {{Lab3_report.docx|Lab3 Report (DOC)}}| {{lab3_supplement.pdf|Lab3 Supplement (PDF)}} \\ {{lab3_supplement.pptx|Lab3 Supplement (PPT)}} |09.04 | | | Lab 3: Verilog for Combinatorial Circuits |23.03 |24.03 |26.03| {{Lab3_manual.pdf|Lab3 Manual}} \\ {{Lab3_report.pdf|Lab3 Report (PDF)}} \\ {{Lab3_report.docx|Lab3 Report (DOC)}}| {{lab3_supplement.pdf|Lab3 Supplement (PDF)}} \\ {{lab3_supplement.pptx|Lab3 Supplement (PPT)}} |09.04 | | ||
| Lab 4: Finite State Machines |30.03|31.03|16.04| {{Lab4_manual.pdf|Lab4 Manual}} \\ {{Lab4_report.pdf|Lab4 Report (PDF)}} \\ {{Lab4_report.docx|Lab4 Report (DOC)}} | {{lab4_supplement.pdf|Lab4 Supplement (PDF)}} \\ {{lab4_supplement.pptx|Lab4 Supplement (PPT)}} |30.04| | | Lab 4: Finite State Machines |30.03|31.03|16.04| {{Lab4_manual.pdf|Lab4 Manual}} \\ {{Lab4_report.pdf|Lab4 Report (PDF)}} \\ {{Lab4_report.docx|Lab4 Report (DOC)}} | {{lab4_supplement.pdf|Lab4 Supplement (PDF)}} \\ {{lab4_supplement.pptx|Lab4 Supplement (PPT)}} |30.04| | ||
- | | Lab 5: Implementing an ALU |13.04|14.04|23.04| {{Lab5_manual.pdf|Lab5 Manual}} \\ {{Lab5_report.pdf|Lab5 Report (PDF)}} \\ {{Lab5_report.docx|Lab5 Report (DOC)}} | {{lab5_supplement.pdf|Lab5 Supplement (PDF)}} \\ {{lab5_supplement.pptx|Lab5 Supplement (PPT)}} |07.05| | + | | Lab 5: Implementing an ALU |13.04|14.04|23.04| {{digitaldesign-s21-lab5_manual_afterlab.pdf|Lab5 Manual}} \\ {{digitaldesign-s21-lab5_report_afterlab.pdf|Lab5 Report (PDF)}} \\ {{digitaldesign-s21-lab5_report_afterlab.docx|Lab5 Report (DOC)}} | {{digitaldesign-s21-lab5_supplement_afterlab.pdf|Lab5 Supplement (PDF)}} \\ {{digitaldesign-s21-lab5_supplement_afterlab.pptx|Lab5 Supplement (PPT)}} |07.05| |
- | | Lab 6: Testing the ALU |20.04|21.04|30.04| | |14.05| | + | | Lab 6: Testing the ALU |20.04 |21.04 |30.04| |
- | | Lab 7: Writing Assembly Code |27.04|28.04|07.05| | |21.05| | + | | Lab 7: Writing Assembly Code |27.04|28.04|07.05| |
- | | Lab 8: Full System Integration (Part I) |04.05|05.05|14.05| | |28.05| | + | | Lab 8: Full System Integration (Part I) |04.05|05.05|14.05| |
- | | Lab 8: Full System Integration (Part II) |11.05|12.05|21.05| | |04.06| | + | | Lab 8: Full System Integration (Part II) |11.05|12.05|21.05|{{lab8_report-session2.pdf|Lab8.2 Report (PDF)}} \\ {{lab8_report-session2.docx|Lab8.2 Report (DOC)}} |{{digitaldesign-s21-lab8.2_supplement_afterlab.pdf|Lab8.2 Supplement (PDF)}} \\ {{digitaldesign-s21-lab8.2_supplement_afterlab.pptx|Lab8.2 Supplement (PPT)}} |
| Lab 9: The Performance of MIPS |18.05|19.05|28.05| | |11.06| | | Lab 9: The Performance of MIPS |18.05|19.05|28.05| | |11.06| | ||
| Extra Session |25.05|26.05|04.06| | | | | Extra Session |25.05|26.05|04.06| | | |
labs.txt · Last modified: 2021/05/17 18:14 by gagsingh