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Lab Schedule

  • You will work in groups of 2. There are 9 labs in total (lab 8 spans two sessions).
  • You will do hands-on exercises and be required to demonstrate your implementation.
  • The required demonstration is mentioned in the lab exercises sheet at the end of the manual. Only the demonstration is required, you do not need to hand in the sheet.
  • The deadline for each lab (in-class evaluation) is the next lab session. At the beginning of the next lab session, you should ask a TA to review your lab. For instance, if your group is Tuesday, the deadline for Lab 1 is Tuesday, 10.03.
  • The deadline for each lab report is in the following table. This is a hard deadline.
Lab Tuesday Wednesday Friday (2 sessions) Manual, Report and Files Slides Deadline (Lab Report)
Lab 1: Drawing a Basic Circuit 09.0310.0312.03Lab1 Manual
Lab1 Report (PDF)
Lab1 Report (DOC)
Lab1 Supplement (PDF)
Lab1 Supplement (PPT)
26.03
Lab 2: Mapping Your Circuit to FPGA 16.0317.0319.03 Lab2 Manual
Lab2 Report (PDF)
Lab2 Report (DOC)
Lab2 Supplement (PDF)
Lab2 Supplement (PPT)
02.04
Lab 3: Verilog for Combinatorial Circuits 23.03 24.03 26.03 Lab3 Manual
Lab3 Report (PDF)
Lab3 Report (DOC)
Lab3 Supplement (PDF)
Lab3 Supplement (PPT)
09.04
Lab 4: Finite State Machines 30.0331.0316.04 Lab4 Manual
Lab4 Report (PDF)
Lab4 Report (DOC)
Lab4 Supplement (PDF)
Lab4 Supplement (PPT)
30.04
Lab 5: Implementing an ALU 13.0414.0423.04 Lab5 Manual
Lab5 Report (PDF)
Lab5 Report (DOC)
Lab5 Supplement (PDF)
Lab5 Supplement (PPT)
07.05
Lab 6: Testing the ALU 20.04 21.04 30.04 Lab6 Manual
Lab6 Files
Lab6 Report (PDF)
Lab6 Report (DOC)
Lab6 Supplement (PDF)
Lab6 Supplement (PPT)
14.05
Lab 7: Writing Assembly Code 27.0428.0407.05 Lab7 Manual
Lab7 Files
Lab7 Report (PDF)
Lab7 Report (DOC)
Lab7 Supplement (PDF)
Lab7 Supplement (PPT)
21.05
Lab 8: Full System Integration (Part I) 04.0505.0514.05 Lab8 Manual
Lab8 Files
Lab8.1 Report (PDF)
Lab8.1 Report (DOC)
Lab8.1 Supplement (PDF)
Lab8.1 Supplement (PPT)
28.05
Lab 8: Full System Integration (Part II) 11.0512.0521.05Lab8.2 Report (PDF)
Lab8.2 Report (DOC)
04.06
Lab 9: The Performance of MIPS 18.0519.0528.05 11.06
Extra Session 25.0526.0504.06

Working with the FPGA Board

For this course, we use the software Vivado for FPGA programming. The computers in the lab rooms are already installed with the necessary software. To use your own computer, you can refer to the following instructions: https://reference.digilentinc.com/learn/programmable-logic/tutorials/basys-3-getting-started/start

You can also find examples for the Basys 3 board and a master constraint file here: https://reference.digilentinc.com/reference/programmable-logic/basys-3/start

Help

For technical questions, please post in Piazza, using the corresponding lab folder. Our assistants will try to respond quickly. For other inquiries please email us at digitaltechnik@lists.inf.ethz.ch.

Frequently Asked Questions:

Q: Can I use my lab grades from previous years?
A: Yes. You can find your past lab grades in Moodle (Spring 2020).

Q: Can I use my lab grades from previous years and still do the labs?
A: Sure! Choose this option on the sign-up form that we provide in Moodle.

Q: Can I do the labs and decide at the end of the semester whether to use my grades from previous years?
A: No. You need to decide at the beginning of the semester. We provide a survey in Moodle.

Q: I don't have a partner. What do I do?
A: Make new friends and find one:) Otherwise we will pair you with another person who has not found a partner.

Q: Can we have groups of three students?
A: No. We will pair you with another person who has not found a partner. Groups of two are much better for your learning experience instead of three so we will only make exceptions if absolutely necessary.

Q: Are the lab sessions held in-person or online?
A: All lab sessions will be online for this semester until a further notice.

labs.1620641981.txt.gz · Last modified: 2021/05/10 12:19 by mnika