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readings [2021/07/04 11:46]
haimao [Lecture 26a (04.06 Fri.)]
readings [2021/07/05 14:39]
jispark [Lecture 10 (20.03 Fri.)]
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   * D. Harris and S. Harris, "​Chapters 2.9 and 3.5: Timing and Verification."​   * D. Harris and S. Harris, "​Chapters 2.9 and 3.5: Timing and Verification."​
   * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks."​ (Start)   * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks."​ (Start)
- 
  
  
 ===== Lecture 8 (19.03 Fri.) ===== ===== Lecture 8 (19.03 Fri.) =====
  
-=== Required video lecture assignments (Lecture ​7): ===+=== Required video lecture assignments (Lecture ​8): ===
   * {{youtube>​link:​kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}}   * {{youtube>​link:​kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}}
   * {{youtube>​link:​mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}}   * {{youtube>​link:​mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}}
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 ~~NOCACHE~~ ~~NOCACHE~~
-====== Readings ====== 
-===== Books ===== 
-  * {{patt-and-patel.zip|Y.N. Patt and S.J. Patel, "​Introduction to Computing Systems."​}} 
-    * {{pp-appendixa.pdf|"​Appendix A: The LC-3b ISA."​}} ​ 
-    * {{pp-appendixc.pdf|"​Appendix C: The Microarchitecture of the LC-3b, Basic Machine."​}} ​ 
-    * {{lc3b-figures.pdf|"​LC-3b Figures."​}} ​ 
-  * {{http://​www.sciencedirect.com/​science/​book/​9780123944245|D. Harris and S. Harris, "​Digital Design and Computer Architecture (2nd Edition)."​}} ​ 
-  * {{https://​www.sciencedirect.com/​science/​book/​9780123704979|D. Harris and S. Harris, "​Digital Design and Computer Architecture (1st Edition)."​}} H&H textbooks are available online (through the ETH network or the ETH VPN). 
  
-===== Lecture 1 (20.02 Thu.) ===== 
-=== Reading assignments (Lecture 1): === 
-  * D. Harris and S. Harris, "​Chapter 1: From Zero to One. Digital Design and Computer Architecture."​ 
-  * Y.N. Patt and S.J. Patel, "​Chapter 1: Welcome Aboard. Introduction to Computing Systems."​ 
-  * Y.N. Patt and S.J. Patel, "​Chapter 2: Bits, Data Types, and Operations. Introduction to Computing Systems."​ 
-  * {{Reading-Week1_BinaryNumbers.pdf|"​Binary Numbers (pdf)."​}} {{Reading-Week1_BinaryNumbers.pptx|"​Binary Numbers (pptx)."​}} 
  
-=== Suggested readings (Lecture 1): === 
-  * {{https://​en.wikipedia.org/​wiki/​The_Structure_of_Scientific_Revolutions| T.S. Kuhn, "The Structure of Scientific Revolutions,"​ 1962}} 
  
-=== Mentioned in Lecture 1: === 
-  * {{Numerical.Methods.For.Scientists.And.Engineers_2ed_Hamming_0486652416.pdf|R.W. Hamming, "​Numerical Methods for Scientists and Engineers,​” 1962.}} 
-  * {{indcperf.pdf|N.P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers, R. Boyle, P.-L. Cantin, C. Chao, C. Clark, J. Coriell, M. Daley, M. Dau, J. Dean, B. Gelb, T.V. Ghaemmaghami,​ R. Gottipati, W. Gulland, R. Hagmann, C.R. Ho, D. Hogberg, J. Hu, R. Hundt, D. Hurt, J. Ibarz, A. Jaffey, A. Jaworski, A. Kaplan, H. Khaitan, D. Killebrew, A. Koch, N. Kumar, S. Lacy, J. Laudon, J. Law, D. Le, C. Leary, Z. Liu, K. Lucke, A. Lundin, G. MacKean, A. Maggiore, M. Mahony, K. Miller, R. Nagarajan, R. Narayanaswami,​ R. Ni, K. Nix, T. Norrie, M. Omernick, N. Penukonda, A. Phelps, J. Ross, M. Ross, A. Salek, E. Samadiani, C. Severn, G. Sizikov, M. Snelham, J. Souter, D. Steinberg, A. Swing, M. Tan, G. Thorson, B. Tian, H. Toma, E. Tuttle, V. Vasudevan, R. Walter, W. Wang, E. Wilcox, D.H. Yoon, "​In-Datacenter Performance Analysis of a Tensor Processing Unit,” ISCA 2017.}} ​ 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_isca09.pdf|B.C. Lee, E. Ipek, O. Mutlu, D. Burger, "​Architecting Phase Change Memory as a Scalable DRAM Alternative,"​ ISCA 2009}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​pcm_ieee_micro10.pdf|B. C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, and D. Burger "​Phase-Change Technology and the Future of Main Memory"​ IEEE Micro Top Picks 2010}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf| Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,"​ ISCA, 2015.}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf| A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun,​ E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan,​ and O. Mutlu, "​Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,​” ASPLOS, 2018.}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "​Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,"​ ISCA 2014}} 
-  * {{https://​arxiv.org/​pdf/​1904.09724.pdf|O. Mutlu, J. S. Kim, RowHammer: A Retrospective,"​ arXiv, 2019}} 
-  * {{https://​arxiv.org/​pdf/​1711.08774.pdf|D. Senol Cali, J.S. Kim, S. Ghose, C. Alkan, and O. Mutlu, “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,​” Briefings in Bioinformatics,​ 2018}} 
  
  
-===== Lecture 2a (21.02 Fri.) ===== 
  
-=== Reading assignments (Lecture 2a): === 
-  * D. Harris and S. Harris, "​Chapter 1: From Zero to One. Digital Design and Computer Architecture."​ 
-  * Y.N. Patt and S.J. Patel, "​Chapter 1: Welcome Aboard. Introduction to Computing Systems."​ 
-  * Y.N. Patt and S.J. Patel, "​Chapter 2: Bits, Data Types, and Operations. Introduction to Computing Systems."​ 
-  * {{Reading-Week1_BinaryNumbers.pdf|"​Binary Numbers (pdf)."​}} {{Reading-Week1_BinaryNumbers.pptx|"​Binary Numbers (pptx)."​}} 
  
-=== Mentioned in Lecture 2a: === 
-  * {{indcperf.pdf|N.P. Jouppi, C. Young, N. Patil, D. Patterson, G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Boden, A. Borchers, R. Boyle, P.-L. Cantin, C. Chao, C. Clark, J. Coriell, M. Daley, M. Dau, J. Dean, B. Gelb, T.V. Ghaemmaghami,​ R. Gottipati, W. Gulland, R. Hagmann, C.R. Ho, D. Hogberg, J. Hu, R. Hundt, D. Hurt, J. Ibarz, A. Jaffey, A. Jaworski, A. Kaplan, H. Khaitan, D. Killebrew, A. Koch, N. Kumar, S. Lacy, J. Laudon, J. Law, D. Le, C. Leary, Z. Liu, K. Lucke, A. Lundin, G. MacKean, A. Maggiore, M. Mahony, K. Miller, R. Nagarajan, R. Narayanaswami,​ R. Ni, K. Nix, T. Norrie, M. Omernick, N. Penukonda, A. Phelps, J. Ross, M. Ross, A. Salek, E. Samadiani, C. Severn, G. Sizikov, M. Snelham, J. Souter, D. Steinberg, A. Swing, M. Tan, G. Thorson, B. Tian, H. Toma, E. Tuttle, V. Vasudevan, R. Walter, W. Wang, E. Wilcox, D.H. Yoon, "​In-Datacenter Performance Analysis of a Tensor Processing Unit,” ISCA 2017.}} ​ 
  
-===== Lecture 2b (21.02 Fri.) ===== 
  
-=== Suggested readings (Lecture 2b): === 
  
-  * {{bstj29-2-147.pdf|R.W. Hamming, "Error Detecting and Error Correcting Codes,"​ Bell System Technical Journal, 1950.}} 
-  * {{youandyourresearch.pdf|R.W. Hamming, "You and Your Research,"​ Transcription of the Bell Communications Research Colloquium Seminar, 1986.}} 
  
- 
-=== Mentioned in Lecture 2b: === 
- 
-  * {{https://​googleprojectzero.blogspot.ch/​2018/​01/​reading-privileged-memory-with-side.html | J. Horn, "​Project Zero Reading Privileged Memory with a Side-channel,"​ Google Project Zero, 2018}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-row-hammer_isca14.pdf|Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu, "​Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,"​ ISCA 2014}} 
-  * {{https://​googleprojectzero.blogspot.ch/​2015/​03/​exploiting-dram-rowhammer-bug-to-gain.html | M. Seaborn and T. Dullien, "​Exploiting the DRAM rowhammer bug to gain kernel privileges,"​ Google Project Zero, 2015}} 
-  * {{10.1007-978-3-319-40667-1_15.pdf| D. Gruss, C. Maurice, S. Mangard, "​Rowhammer.js:​ A Remote Software-Induced Fault Attack in JavaScript,"​ DIMVA 2016}} 
-  * {{p1675-van-der-veen.pdf| V. van der Veen, Y. Fratantonio,​ M. Lindorfer, D. Gruss, C. Maurice, G. Vigna, H. Bos, K. Razavi, C. Giuffrida, "​Drammer:​ Deterministic Rowhammer Attacks on Mobile Platforms,"​ CCS 2016}} 
-  * {{1805.04956-2.pdf|Moritz Lipp, Misiker Tadesse Aga, Michael Schwarz, Daniel Gruss, Clémentine Maurice, Lukas Raab, "​Niethammer:​ Inducing Rowhammer Faults through Network Requests",​ arXiv 2018}} 
-  * {{20190603-rambleed-web-2.pdf|Andrew Kwong, Daniel Genkin, Daniel Gruss, Yuval Yarom, "​RAMBleed:​ Reading Bits in Memory Without Accessing Them", IEEE S&P 2020}} 
-  * {{1706.08642-2.pdf|Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu, "Error Characterization,​ Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives",​ Proceddings of the IEEE 2016}} 
-  * {{woot17-paper-kurmus-2.pdf|Anil Kurmus, Nikolas Ioannou, Matthias Neugschwandtner,​ Nikolaos Papandreou, Thomas Parnell, "From random block corruption to privilege escalation: A filesystem attack vector for rowhammer-like attacks",​ WOOT 2017}} 
-  * {{p382-lamport.pdf| L. Lamport, R. Showtak, M. Pease, "The Byzantine Generals Problem,"​ ACM TOPLAS, 1982}} 
-  * {{rowhammer_retrospective.pdf|O. Mutlu, J. Kim, "​RowHammer:​ A Retrospective,"​ TCAD 2019}} 
- 
-===== Lecture 3a (27.02 Thu.) ===== 
-=== Suggested readings (Lecture 3a): ===  
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​raidr-dram-refresh_isca12.pdf|J. Liu, B. Jaiyen, R. Veras, O. Mutlu, "​RAIDR:​ Retention-Aware Intelligent DRAM Refresh,"​ ISCA 2012}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​mph_usenix_security07.pdf|Thomas Moscibroda and Onur Mutlu, "​Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems"​ USENIX Security 2007}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​memory-scaling_memcon13.pdf| Onur Mutlu, "​Memory Scaling: A Systems Architecture Perspective,"​ MemCon 2013}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​dram-access-refresh-parallelization_hpca14.pdf|K. Chang, D. Lee, Z. Chishti, A. Alameldeen, C. Wilkerson, Y. Kim, O. Mutlu, "​Improving DRAM Performance by Parallelizing Refreshes with Accesses,"​ HPCA 2014}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​stfm_micro07.pdf|O. Mutlu and T. Moscibroda, "​Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors,"​ MICRO 2007}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​parbs_isca08.pdf| Onur Mutlu and Thomas Moscibroda, "​Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems"​}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​memory-channel-partitioning-micro11.pdf|S.P. Muralidhara,​ L. Subramanian,​ O. Mutlu, M. Kandemir, T. Moscibroda, “Reducing Memory Interference in Multicore Systems via Application-aware Memory Channel Partitioning,​” MICRO 2011}} 
- 
-===== Lecture 3b (27.02 Thu.) ===== 
-=== Mentioned in Lecture 3b: === 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, C. Alkan, "​GateKeeper:​ A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,” Bioinformatics,​ 2017}} 
-  * {{https://​people.inf.ethz.ch/​omutlu/​pub/​softMC_hpca17.pdf| Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu, "​SoftMC:​ A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies,"​ HPCA 2017 }} 
-  * {{https://​arxiv.org/​pdf/​1706.08642.pdf| Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, "Error Characterization,​ Mitigation, and Recovery in Flash Memory Based Solid State Drives,"​ Proceedings of the IEEE, Sept. 2017}} 
- 
- 
-===== Lecture 4 (28.02 Fri.) ===== 
-=== Video lecture assignment (Lecture 4): === 
-  * {{youtube>​link:​kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} 
- 
-=== Reading assignments (Lecture 4): === 
-  * D. Harris and S. Harris, "​Chapter 2: Combinational Logic Design."​ 
-  * Y.N. Patt and S.J. Patel, "​Chapter 3: Digital Logic Structures."​ 
- 
-=== Mentioned in Lecture 4: === 
-   * {{gordon_moore_1965_article.pdf| G.E. Moore. "​Cramming more components onto integrated circuits,"​ Electronics magazine, 1965}} 
-   * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the 
-Logical Design of an Electronic Computing Instrument,​” The Origins of Digital Computers, 1946}} 
- 
-===== Lecture 5 (05.03 Thu.) ===== 
-=== Video lecture assignment (Lecture 5): === 
-  * {{youtube>​link:​kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} 
- 
-=== Reading assignments (Lecture 5): === 
-  * D. Harris and S. Harris, "​Chapter 3: Sequential Logic."​ 
-  * D. Harris and S. Harris, "​4.1-4.3 and 4.5: Hardware Description Languages and Verilog."​ 
-  * Y.N. Patt and S.J. Patel, "3.4 until end of Chapter 3: Sequential Logic."​ 
- 
-=== Mentioned in Lecture 5: === 
-  * {{boole.pdf| George Boole. "The Mathematical Analysis of Logic,"​ 1847}} 
- 
-===== Lecture 6 (06.03 Fri.) ===== 
-=== Video lecture assignment (Lecture 5): === 
-  * {{youtube>​link:​0ks0PeaOUjE| Onur Mutlu - Design of Digital Circuits - Lecture 5. Combinational Logic II - ETH Zurich - Spring 2019.}} 
-  * {{youtube>​link:​ozs18ARNG6s| Onur Mutlu - Design of Digital Circuits - Lecture 6. Sequential Logic Design - ETH Zurich - Spring 2019.}} 
- 
-=== Reading assignments (Lecture 6): === 
-  * Y.N. Patt and S.J. Patel, "3 until 3.3: Combinational Logic."​ 
-  * D. Harris and S. Harris, "​Chapter 2: Combinational Logic."​ 
-  * D. Harris and S. Harris, "​Chapter 3: Sequential Logic."​ 
-  * D. Harris and S. Harris, "​Chapter 4: Hardware Description Languages and Verilog."​ 
-  * D. Harris and S. Harris, "​Chapters 2.9 and 3.5 + (start Chapter 5): Timing and Verification."​ 
-  * Y.N. Patt and S.J. Patel, "3.4 until end: Sequential Logic."​ 
- 
-=== Mentioned in Lecture 6: === 
-  * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) 
- 
-===== Lecture 7a (12.03 Thu.) ===== 
-=== Video lecture assignment (Lecture 7a) : === 
-   * {{youtube>​link:​kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture ​  15 May 2017 }} 
- 
-=== Extra Assignment: Moore'​s Law (Lecture 7a)  === 
- ​{{gordon_moore_1965_article.pdf| G.E. Moore. "​Cramming more components onto integrated circuits,"​ Electronics magazine, 1965}} 
- 
-=== Reading assignments (Lecture 7a): ===  
- 
-  * D. Harris and S. Harris, "​Chapters 2.9 and 3.5: Timing and Verification."​ 
-  * D. Harris and S. Harris, "​Chapter 4: Hardware Description Languages."​ (Full) 
-  * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks."​ (Start) 
-  * Y.N. Patt and S.J. Patel, Chapters 1-3 
- 
- 
-===== Lecture 7b (12.03 Thu.) ===== 
-=== Reading assignments (Lecture 7b): ===  
-  * D. Harris and S. Harris, "​Chapters 2.9 and 3.5: Timing and Verification."​ 
-  * D. Harris and S. Harris, "​Chapter 4: Hardware Description Languages."​ (Full) 
-  * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks."​ (Start) 
-  * Y.N. Patt and S.J. Patel, Chapters 1-3 
- 
-===== Lecture 8 (13.03 Fri.) ===== 
-=== Reading assignments (Lecture 8): ===  
-  * D. Harris and S. Harris, “Chapters 2.9 and 3.5: Timing and Verification.” 
-  * D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog.” 
-  * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks."​ (Start) 
- 
-=== Suggested readings (Lecture 8): ===  
-  * {{Gronowski.pdf|P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, "​High-Performance Microprocessor Design,"​ IEEE Journal of Solid-State Circuits 1998}} 
-  * {{GLSVLSI_10_Clock_mesh.pdf|A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, "​Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis,"​ GLSVLSI 2010}} 
- 
-===== Lecture 9 (19.03 Thu.) ===== 
-=== Reading assignments (Lecture 9): ===  
-  * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” 
-  * Y.N. Patt and S.J. Patel, “Chapter 5: The LC-3.” 
-  * Y.N. Patt and S.J. Patel, “Chapter 6: Programming.” 
-  * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, "​Appendix A: The LC-3b ISA."​}} ​ 
-  * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, "​Appendix C: The Microarchitecture of the LC-3b, Basic Machine."​}} 
-  * D. Harris and S. Harris, “Chapter 6: Architecture.” 
-  * D. Harris and S. Harris, “Appendix B: MIPS Instructions.” 
- 
-=== Suggested readings (Lecture 9): ===  
-  * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) 
- 
-=== Mentioned in Lecture 9: === 
-  * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,​” The Origins of Digital Computers, 1946}} 
  
  
-===== Lecture 10 (20.03 Fri.) ===== 
-=== Reading assignments (Lecture 10): ===  
-     * Y.N. Patt and S.J. Patel, "​Chapter 4: The Von Neumann Model" ​ 
-     * Y.N. Patt and S.J. Patel, "​Chapter 5: The LC-3" ​ 
-     * Y.N. Patt and S.J. Patel, "​Chapter 6: Programming"​ 
-     * Y.N. Patt and S.J. Patel, {{pp-appendixa.pdf|"​Appendix A: The LC-3b ISA."​}} ​ 
-     * Y.N. Patt and S.J. Patel, {{pp-appendixc.pdf|"​Appendix C: The Microarchitecture of the LC-3b, Basic Machine."​}} ​ 
-    * D. Harris and S. Harris, "​Chapter 6: Architecture"​ 
-    * D. Harris and S. Harris, "​Appendix B: MIPS Instructions"​ 
  
-=== Suggested readings (Lecture 10): ===  
-  * D. Harris and S. Harris, "​Chapter 5: Digital Building Blocks"​ (especially 5.1, 5.2, 5.4, 5.5) 
  
 ===== Lecture 11 (26.03 Thu.) ===== ===== Lecture 11 (26.03 Thu.) =====
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   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_dissertation.pdf| Onur Mutlu, "​Efficient Runahead Execution Processors,​” Ph.D. Dissertation,​ HPS Technical Report, TR-HPS-2006-007,​ July 2006.   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​mutlu_dissertation.pdf| Onur Mutlu, "​Efficient Runahead Execution Processors,​” Ph.D. Dissertation,​ HPS Technical Report, TR-HPS-2006-007,​ July 2006.
 Nominated for the ACM Doctoral Dissertation Award by the University of Texas at Austin.}} Nominated for the ACM Doctoral Dissertation Award by the University of Texas at Austin.}}
-  * {{https://​www.youtube.com/​watch?​v=zPewo6IaJ_8&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=34 ​| Computer Architecture - Lecture 19aExecution-Based Prefetching ​(ETH Zürich, ​Fall 2020)}}+  * {{youtube>link:zPewo6IaJ_8| Computer Architecture - Lecture 19a Execution-Based Prefetching ​ETH Zurich - Fall 2020}}
   * {{youtube>​link:​KFCOecRQTIc| Onur Mutlu - Runahead Execution - A Short Retrospective - HPCA Test of Time Award Talk - HPCA 2021}}   * {{youtube>​link:​KFCOecRQTIc| Onur Mutlu - Runahead Execution - A Short Retrospective - HPCA Test of Time Award Talk - HPCA 2021}}
   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf| A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun,​ E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan,​ and O. Mutlu, "​Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,​” ASPLOS, 2018.}}   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf| A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun,​ E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan,​ and O. Mutlu, "​Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks,​” ASPLOS, 2018.}}
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   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf| Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,"​ ISCA, 2015.}}   * {{https://​people.inf.ethz.ch/​omutlu/​pub/​tesseract-pim-architecture-for-graph-processing_isca15.pdf| Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, "A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing,"​ ISCA, 2015.}}
   * {{https://​arxiv.org/​pdf/​1903.03988.pdf| Onur Mutlu, Saugata Ghose, Juan Gomez-Luna, and Rachata Ausavarungnirun,​ "A Modern Primer on Processing in Memory”, Invited Book Chapter in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann, Springer, to be published in 2021.}}   * {{https://​arxiv.org/​pdf/​1903.03988.pdf| Onur Mutlu, Saugata Ghose, Juan Gomez-Luna, and Rachata Ausavarungnirun,​ "A Modern Primer on Processing in Memory”, Invited Book Chapter in Emerging Computing: From Devices to Systems - Looking Beyond Moore and Von Neumann, Springer, to be published in 2021.}}
-  * {{https://​arxiv.org/​pdf/​1907.12947.pdf| Saugata Ghose, Amirali Boroumand, Jeremie S. Kim, Juan Gomez-Luna, and Onur Mutlu, "​Processing-in-Memory:​ A Workload-Driven Perspective”,​ Invited Article in IBM Journal of Research & Development,​ Special Issue on Hardware for Artificial Intelligence,​ to appear in November 2019.}} +  * {{https://​arxiv.org/​pdf/​1907.12947.pdf| Saugata Ghose, Amirali Boroumand, Jeremie S. Kim, Juan Gomez-Luna, and Onur Mutlu, "​Processing-in-Memory:​ A Workload-Driven Perspective”,​ Invited Article in IBM Journal of Research & Development,​ Special Issue on Hardware for Artificial Intelligence,​ to appear in November 2019.}} 
-  * {{https://​www.youtube.com/​watch?​v=Sscy1Wrr22A&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=26  ​| Computer Architecture - Lecture 12dReal Processing-in-DRAM with UPMEM (ETH Zürich, ​Fall 2020)}}+  * {{youtube>​link:​Sscy1Wrr22A&​t=2s| Computer Architecture - Lecture 12d Real Processing-in-DRAM with UPMEM ETH Zurich - Fall 2020}}
   * {{https://​arxiv.org/​pdf/​2105.03814.pdf| Gómez-Luna,​ Juan, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, and Onur Mutlu. "​Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture”,​ arXiv,​ 2021.}}   * {{https://​arxiv.org/​pdf/​2105.03814.pdf| Gómez-Luna,​ Juan, Izzat El Hajj, Ivan Fernandez, Christina Giannoula, Geraldo F. Oliveira, and Onur Mutlu. "​Benchmarking a New Paradigm: An Experimental Analysis of a Real Processing-in-Memory Architecture”,​ arXiv,​ 2021.}}
   * {{https://​arxiv.org/​pdf/​2105.03814.pdf| Oliveira, Geraldo F., Juan Gómez-Luna,​ Lois Orosa, Saugata Ghose, Nandita Vijaykumar, Ivan Fernandez, Mohammad Sadrosadati,​ and Onur Mutlu. "​DAMOV:​ A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks”,​ arXiv,​ 2021.}}   * {{https://​arxiv.org/​pdf/​2105.03814.pdf| Oliveira, Geraldo F., Juan Gómez-Luna,​ Lois Orosa, Saugata Ghose, Nandita Vijaykumar, Ivan Fernandez, Mohammad Sadrosadati,​ and Onur Mutlu. "​DAMOV:​ A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks”,​ arXiv,​ 2021.}}
-  * {{https://​www.youtube.com/​watch?​v=oGcZAGwfEUE&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=12| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 6Computation in Memory ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:5YKvtNM6XzY| Onur Mutlu - Computer Architecture ​Lecture 6 Computation in Memory ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=j2GIigqn1Qw&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=13| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 7Near-Data Processing ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:​j2GIigqn1Qw| Onur Mutlu - Computer Architecture ​Lecture 7 Near-Data Processing ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=TeG773OgiMQ&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=20| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 11aMemory Controllers ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>link:TeG773OgiMQ| Onur Mutlu - Computer Architecture ​Lecture 11a Memory Controllers ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=AlE1rD9G_YU&list =PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=28| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 15Emerging Memory Technologies ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>link:AlE1rD9G_YU| Onur Mutlu - Computer Architecture ​Lecture 15 Emerging Memory Technologies ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=pmLszWGmMGQ&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=29| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 16aOpportunities ​Challenges of Emerging Memory Technologies ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:​pmLszWGmMGQ| Onur Mutlu - Computer Architecture ​Lecture 16a Opportunities ​and Challenges of Emerging Memory Technologies ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=wNmqQHiEZNk&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=41| Onur Mutlu - Computer Architecture, Fall 2020, Guest LectureIn-Memory ComputingMemory Devices ​Applications ​ (ETH Zürich, ​Fall 2020)}}+  * {{youtube>link:wNmqQHiEZNk| Onur Mutlu - Computer Architecture ​Guest Lecture ​In-Memory Computing-Memory Devices ​and Applications ​ETH Zurich - Fall 2020}}
   * {{ https://​people.inf.ethz.ch/​omutlu/​pub/​AcceleratingGenomeAnalysis_ieeemicro20.pdf | Mohammed Alser, Zulal Bingol, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, and Onur Mutlu, "​Accelerating Genome Analysis: A Primer on an Ongoing Journey,"​ IEEE Micro 2020.}}   * {{ https://​people.inf.ethz.ch/​omutlu/​pub/​AcceleratingGenomeAnalysis_ieeemicro20.pdf | Mohammed Alser, Zulal Bingol, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, and Onur Mutlu, "​Accelerating Genome Analysis: A Primer on an Ongoing Journey,"​ IEEE Micro 2020.}}
-  * {{https://​www.youtube.com/​watch?​v=CrRb32v7SJc&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=5 ​| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 3aIntroduction to Genome Sequence Analysis ​  (ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:​CrRb32v7SJc| Onur Mutlu - Computer Architecture ​Lecture 3a Introduction to Genome Sequence Analysis ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=ygmQpdDTL7o&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=14 ​| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 8Intelligent Genome Analysis ​ (ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:​ygmQpdDTL7o| Onur Mutlu - Computer Architecture ​Lecture 8 Intelligent Genome Analysis ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=XoLpzmN-Pas&​list=PL5Q2soXY2Zi9xidyIgBxUz7xRPS-wisBN&​index=15 ​| Onur Mutlu - Computer Architecture, Fall 2020, Lecture 9aGenASMApproxString Matching Accelerator ​(ETH Zürich, ​Fall 2020)}} +  * {{youtube>​link:​XoLpzmN-Pas| Onur Mutlu - Computer Architecture ​Lecture 9a GenASM-Approx String Matching Accelerator ​ETH Zurich - Fall 2020}} 
-  * {{https://​www.youtube.com/​watch?​v=rgjl8ZyLsAg&​list=PL5Q2soXY2Zi9E2bBVAgCqLgwiDRQDTyId  +  * {{youtube>link:rgjl8ZyLsAg| Accelerating Genomics Project Course ​Fall 2020 Lecture 1}}
-| Accelerating Genomics Project CourseFall 2020Lecture 1}}+
readings.txt · Last modified: 2021/07/05 14:39 by jispark