readings
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readings [2021/07/05 14:30] jispark [Lecture 3a (27.02 Thu.)] |
readings [2021/07/05 14:39] jispark [Lecture 10 (20.03 Fri.)] |
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| * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | ||
| * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | |||
| ===== Lecture 8 (19.03 Fri.) ===== | ===== Lecture 8 (19.03 Fri.) ===== | ||
| - | === Required video lecture assignments (Lecture 7): === | + | === Required video lecture assignments (Lecture 8): === |
| * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | ||
| * {{youtube>link:mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}} | * {{youtube>link:mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}} | ||
| Line 257: | Line 256: | ||
| - | ===== Lecture 3b (27.02 Thu.) ===== | ||
| - | === Mentioned in Lecture 3b: === | ||
| - | * {{https://people.inf.ethz.ch/omutlu/pub/gatekeeper_FPGA-genome-prealignment-accelerator_bionformatics17.pdf|M. Alser, H. Hassan, H. Xin, O. Ergin, O. Mutlu, C. Alkan, "GateKeeper: A New Hardware Architecture for Accelerating Pre-Alignment in DNA Short Read Mapping,” Bioinformatics, 2017}} | ||
| - | * {{https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf| Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu, "SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies," HPCA 2017 }} | ||
| - | * {{https://arxiv.org/pdf/1706.08642.pdf| Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, and Onur Mutlu, "Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives," Proceedings of the IEEE, Sept. 2017}} | ||
| - | ===== Lecture 4 (28.02 Fri.) ===== | ||
| - | === Video lecture assignment (Lecture 4): === | ||
| - | * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | ||
| - | |||
| - | === Reading assignments (Lecture 4): === | ||
| - | * D. Harris and S. Harris, "Chapter 2: Combinational Logic Design." | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 3: Digital Logic Structures." | ||
| - | |||
| - | === Mentioned in Lecture 4: === | ||
| - | * {{gordon_moore_1965_article.pdf| G.E. Moore. "Cramming more components onto integrated circuits," Electronics magazine, 1965}} | ||
| - | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the | ||
| - | Logical Design of an Electronic Computing Instrument,” The Origins of Digital Computers, 1946}} | ||
| - | |||
| - | ===== Lecture 5 (05.03 Thu.) ===== | ||
| - | === Video lecture assignment (Lecture 5): === | ||
| - | * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | ||
| - | |||
| - | === Reading assignments (Lecture 5): === | ||
| - | * D. Harris and S. Harris, "Chapter 3: Sequential Logic." | ||
| - | * D. Harris and S. Harris, "4.1-4.3 and 4.5: Hardware Description Languages and Verilog." | ||
| - | * Y.N. Patt and S.J. Patel, "3.4 until end of Chapter 3: Sequential Logic." | ||
| - | |||
| - | === Mentioned in Lecture 5: === | ||
| - | * {{boole.pdf| George Boole. "The Mathematical Analysis of Logic," 1847}} | ||
| - | |||
| - | ===== Lecture 6 (06.03 Fri.) ===== | ||
| - | === Video lecture assignment (Lecture 5): === | ||
| - | * {{youtube>link:0ks0PeaOUjE| Onur Mutlu - Design of Digital Circuits - Lecture 5. Combinational Logic II - ETH Zurich - Spring 2019.}} | ||
| - | * {{youtube>link:ozs18ARNG6s| Onur Mutlu - Design of Digital Circuits - Lecture 6. Sequential Logic Design - ETH Zurich - Spring 2019.}} | ||
| - | |||
| - | === Reading assignments (Lecture 6): === | ||
| - | * Y.N. Patt and S.J. Patel, "3 until 3.3: Combinational Logic." | ||
| - | * D. Harris and S. Harris, "Chapter 2: Combinational Logic." | ||
| - | * D. Harris and S. Harris, "Chapter 3: Sequential Logic." | ||
| - | * D. Harris and S. Harris, "Chapter 4: Hardware Description Languages and Verilog." | ||
| - | * D. Harris and S. Harris, "Chapters 2.9 and 3.5 + (start Chapter 5): Timing and Verification." | ||
| - | * Y.N. Patt and S.J. Patel, "3.4 until end: Sequential Logic." | ||
| - | |||
| - | === Mentioned in Lecture 6: === | ||
| - | * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) | ||
| - | |||
| - | ===== Lecture 7a (12.03 Thu.) ===== | ||
| - | === Video lecture assignment (Lecture 7a) : === | ||
| - | * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture 15 May 2017 }} | ||
| - | |||
| - | === Extra Assignment: Moore's Law (Lecture 7a) === | ||
| - | {{gordon_moore_1965_article.pdf| G.E. Moore. "Cramming more components onto integrated circuits," Electronics magazine, 1965}} | ||
| - | |||
| - | === Reading assignments (Lecture 7a): === | ||
| - | |||
| - | * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | ||
| - | * D. Harris and S. Harris, "Chapter 4: Hardware Description Languages." (Full) | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | * Y.N. Patt and S.J. Patel, Chapters 1-3 | ||
| - | |||
| - | |||
| - | ===== Lecture 7b (12.03 Thu.) ===== | ||
| - | === Reading assignments (Lecture 7b): === | ||
| - | * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | ||
| - | * D. Harris and S. Harris, "Chapter 4: Hardware Description Languages." (Full) | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | * Y.N. Patt and S.J. Patel, Chapters 1-3 | ||
| - | |||
| - | ===== Lecture 8 (13.03 Fri.) ===== | ||
| - | === Reading assignments (Lecture 8): === | ||
| - | * D. Harris and S. Harris, “Chapters 2.9 and 3.5: Timing and Verification.” | ||
| - | * D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog.” | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | |||
| - | === Suggested readings (Lecture 8): === | ||
| - | * {{Gronowski.pdf|P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, "High-Performance Microprocessor Design," IEEE Journal of Solid-State Circuits 1998}} | ||
| - | * {{GLSVLSI_10_Clock_mesh.pdf|A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, "Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis," GLSVLSI 2010}} | ||
| - | ===== Lecture 9 (19.03 Thu.) ===== | ||
| - | === Reading assignments (Lecture 9): === | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 5: The LC-3.” | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 6: Programming.” | ||
| - | * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, "Appendix A: The LC-3b ISA."}} | ||
| - | * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, "Appendix C: The Microarchitecture of the LC-3b, Basic Machine."}} | ||
| - | * D. Harris and S. Harris, “Chapter 6: Architecture.” | ||
| - | * D. Harris and S. Harris, “Appendix B: MIPS Instructions.” | ||
| - | === Suggested readings (Lecture 9): === | ||
| - | * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) | ||
| - | === Mentioned in Lecture 9: === | ||
| - | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,” The Origins of Digital Computers, 1946}} | ||
| - | ===== Lecture 10 (20.03 Fri.) ===== | ||
| - | === Reading assignments (Lecture 10): === | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 4: The Von Neumann Model" | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 5: The LC-3" | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 6: Programming" | ||
| - | * Y.N. Patt and S.J. Patel, {{pp-appendixa.pdf|"Appendix A: The LC-3b ISA."}} | ||
| - | * Y.N. Patt and S.J. Patel, {{pp-appendixc.pdf|"Appendix C: The Microarchitecture of the LC-3b, Basic Machine."}} | ||
| - | * D. Harris and S. Harris, "Chapter 6: Architecture" | ||
| - | * D. Harris and S. Harris, "Appendix B: MIPS Instructions" | ||
| - | === Suggested readings (Lecture 10): === | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks" (especially 5.1, 5.2, 5.4, 5.5) | ||
| ===== Lecture 11 (26.03 Thu.) ===== | ===== Lecture 11 (26.03 Thu.) ===== | ||
readings.txt · Last modified: 2021/07/05 14:39 by jispark
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