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readings [2021/07/05 12:30] – [Lecture 3b (27.02 Thu.)] jispark | readings [2021/07/05 12:39] (current) – [Lecture 11 (26.03 Thu.)] jispark | ||
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* D. Harris and S. Harris, " | * D. Harris and S. Harris, " | ||
* D. Harris and S. Harris, " | * D. Harris and S. Harris, " | ||
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===== Lecture 8 (19.03 Fri.) ===== | ===== Lecture 8 (19.03 Fri.) ===== | ||
- | === Required video lecture assignments (Lecture | + | === Required video lecture assignments (Lecture |
* {{youtube> | * {{youtube> | ||
* {{youtube> | * {{youtube> | ||
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- | ===== Lecture 4 (28.02 Fri.) ===== | ||
- | === Video lecture assignment (Lecture 4): === | ||
- | * {{youtube> | ||
- | |||
- | === Reading assignments (Lecture 4): === | ||
- | * D. Harris and S. Harris, " | ||
- | * Y.N. Patt and S.J. Patel, " | ||
- | |||
- | === Mentioned in Lecture 4: === | ||
- | * {{gordon_moore_1965_article.pdf| G.E. Moore. " | ||
- | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the | ||
- | Logical Design of an Electronic Computing Instrument, | ||
- | |||
- | ===== Lecture 5 (05.03 Thu.) ===== | ||
- | === Video lecture assignment (Lecture 5): === | ||
- | * {{youtube> | ||
- | |||
- | === Reading assignments (Lecture 5): === | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * Y.N. Patt and S.J. Patel, "3.4 until end of Chapter 3: Sequential Logic." | ||
- | |||
- | === Mentioned in Lecture 5: === | ||
- | * {{boole.pdf| George Boole. "The Mathematical Analysis of Logic," | ||
- | |||
- | ===== Lecture 6 (06.03 Fri.) ===== | ||
- | === Video lecture assignment (Lecture 5): === | ||
- | * {{youtube> | ||
- | * {{youtube> | ||
- | |||
- | === Reading assignments (Lecture 6): === | ||
- | * Y.N. Patt and S.J. Patel, "3 until 3.3: Combinational Logic." | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * Y.N. Patt and S.J. Patel, "3.4 until end: Sequential Logic." | ||
- | |||
- | === Mentioned in Lecture 6: === | ||
- | * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) | ||
- | |||
- | ===== Lecture 7a (12.03 Thu.) ===== | ||
- | === Video lecture assignment (Lecture 7a) : === | ||
- | * {{youtube> | ||
- | |||
- | === Extra Assignment: Moore' | ||
- | | ||
- | |||
- | === Reading assignments (Lecture 7a): === | ||
- | |||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * Y.N. Patt and S.J. Patel, Chapters 1-3 | ||
- | |||
- | |||
- | ===== Lecture 7b (12.03 Thu.) ===== | ||
- | === Reading assignments (Lecture 7b): === | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | * Y.N. Patt and S.J. Patel, Chapters 1-3 | ||
- | |||
- | ===== Lecture 8 (13.03 Fri.) ===== | ||
- | === Reading assignments (Lecture 8): === | ||
- | * D. Harris and S. Harris, “Chapters 2.9 and 3.5: Timing and Verification.” | ||
- | * D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog.” | ||
- | * D. Harris and S. Harris, " | ||
- | |||
- | === Suggested readings (Lecture 8): === | ||
- | * {{Gronowski.pdf|P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, " | ||
- | * {{GLSVLSI_10_Clock_mesh.pdf|A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, " | ||
- | |||
- | ===== Lecture 9 (19.03 Thu.) ===== | ||
- | === Reading assignments (Lecture 9): === | ||
- | * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” | ||
- | * Y.N. Patt and S.J. Patel, “Chapter 5: The LC-3.” | ||
- | * Y.N. Patt and S.J. Patel, “Chapter 6: Programming.” | ||
- | * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, " | ||
- | * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, " | ||
- | * D. Harris and S. Harris, “Chapter 6: Architecture.” | ||
- | * D. Harris and S. Harris, “Appendix B: MIPS Instructions.” | ||
- | === Suggested readings (Lecture 9): === | ||
- | * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) | ||
- | === Mentioned in Lecture 9: === | ||
- | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, | ||
- | ===== Lecture 10 (20.03 Fri.) ===== | ||
- | === Reading assignments (Lecture 10): === | ||
- | * Y.N. Patt and S.J. Patel, " | ||
- | * Y.N. Patt and S.J. Patel, " | ||
- | * Y.N. Patt and S.J. Patel, " | ||
- | * Y.N. Patt and S.J. Patel, {{pp-appendixa.pdf|" | ||
- | * Y.N. Patt and S.J. Patel, {{pp-appendixc.pdf|" | ||
- | * D. Harris and S. Harris, " | ||
- | * D. Harris and S. Harris, " | ||
- | === Suggested readings (Lecture 10): === | ||
- | * D. Harris and S. Harris, " | ||
- | ===== Lecture 11 (26.03 Thu.) ===== | ||
- | === Reading assignments (Lecture 11): === | ||
- | * D. Harris and S. Harris, “Chapter 7: Microarchitecture” (Chapter 7.1, 7.3, 7.4) | ||
- | * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, " | ||
- | * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, " | ||
- | * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” | ||
- | === Suggested readings (Lecture 11): === | ||
- | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument, | ||
- | === Mentioned in Lecture 11: === | ||
- | * {{Dennis.pdf|Dennis and Misunas, “A preliminary architecture for a basic data-flow processor, | ||
- | * {{gurd-cacm85-prototype.pdf|Gurd et al., “The Manchester prototype dataflow computer, | ||
- | * D. Harris and S. Harris, “Chapter 5.2.1" | ||
===== Lecture 12 (15.04 Thu.) ===== | ===== Lecture 12 (15.04 Thu.) ===== |
readings.1625488242.txt.gz · Last modified: 2021/07/05 12:30 by jispark