readings
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readings [2021/07/05 14:32] jispark [Lecture 7b (12.03 Thu.)] |
readings [2021/07/05 14:39] (current) jispark [Lecture 11 (26.03 Thu.)] |
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| * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | * D. Harris and S. Harris, "Chapters 2.9 and 3.5: Timing and Verification." | ||
| * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | |||
| ===== Lecture 8 (19.03 Fri.) ===== | ===== Lecture 8 (19.03 Fri.) ===== | ||
| - | === Required video lecture assignments (Lecture 7): === | + | === Required video lecture assignments (Lecture 8): === |
| * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | * {{youtube>link:kgiZlSOcGFM| Onur Mutlu - Future Computing Architectures - ETH Zurich Inaugural Lecture - 15 May 2017}} | ||
| * {{youtube>link:mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}} | * {{youtube>link:mskTeNnf-i0| Onur Mutlu - Future Computing Platforms - ETH Zurich Inaugural Lecture - 24 Feb 2021}} | ||
| Line 263: | Line 262: | ||
| - | ===== Lecture 8 (13.03 Fri.) ===== | ||
| - | === Reading assignments (Lecture 8): === | ||
| - | * D. Harris and S. Harris, “Chapters 2.9 and 3.5: Timing and Verification.” | ||
| - | * D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog.” | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks." (Start) | ||
| - | |||
| - | === Suggested readings (Lecture 8): === | ||
| - | * {{Gronowski.pdf|P.E. Gronowski, W.J. Bowhill, R.P. Preston, M.K. Gowan, R.L. Allmon, "High-Performance Microprocessor Design," IEEE Journal of Solid-State Circuits 1998}} | ||
| - | * {{GLSVLSI_10_Clock_mesh.pdf|A. Abdelhadi, R. Ginosar, A. Kolodny, E.G. Friedman, "Timing–Driven Variation–Aware Nonuniform Clock Mesh Synthesis," GLSVLSI 2010}} | ||
| - | |||
| - | ===== Lecture 9 (19.03 Thu.) ===== | ||
| - | === Reading assignments (Lecture 9): === | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 5: The LC-3.” | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 6: Programming.” | ||
| - | * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, "Appendix A: The LC-3b ISA."}} | ||
| - | * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, "Appendix C: The Microarchitecture of the LC-3b, Basic Machine."}} | ||
| - | * D. Harris and S. Harris, “Chapter 6: Architecture.” | ||
| - | * D. Harris and S. Harris, “Appendix B: MIPS Instructions.” | ||
| - | |||
| - | === Suggested readings (Lecture 9): === | ||
| - | * D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (note: reading spans multiple lectures) | ||
| - | |||
| - | === Mentioned in Lecture 9: === | ||
| - | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,” The Origins of Digital Computers, 1946}} | ||
| - | |||
| - | |||
| - | ===== Lecture 10 (20.03 Fri.) ===== | ||
| - | === Reading assignments (Lecture 10): === | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 4: The Von Neumann Model" | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 5: The LC-3" | ||
| - | * Y.N. Patt and S.J. Patel, "Chapter 6: Programming" | ||
| - | * Y.N. Patt and S.J. Patel, {{pp-appendixa.pdf|"Appendix A: The LC-3b ISA."}} | ||
| - | * Y.N. Patt and S.J. Patel, {{pp-appendixc.pdf|"Appendix C: The Microarchitecture of the LC-3b, Basic Machine."}} | ||
| - | * D. Harris and S. Harris, "Chapter 6: Architecture" | ||
| - | * D. Harris and S. Harris, "Appendix B: MIPS Instructions" | ||
| - | |||
| - | === Suggested readings (Lecture 10): === | ||
| - | * D. Harris and S. Harris, "Chapter 5: Digital Building Blocks" (especially 5.1, 5.2, 5.4, 5.5) | ||
| - | ===== Lecture 11 (26.03 Thu.) ===== | ||
| - | === Reading assignments (Lecture 11): === | ||
| - | * D. Harris and S. Harris, “Chapter 7: Microarchitecture” (Chapter 7.1, 7.3, 7.4) | ||
| - | * {{pp-appendixa.pdf|Y.N. Patt and S.J. Patel, "Appendix A: The LC-3b ISA."}} | ||
| - | * {{pp-appendixc.pdf|Y.N. Patt and S.J. Patel, "Appendix C: The Microarchitecture of the LC-3b, Basic Machine."}} | ||
| - | * Y.N. Patt and S.J. Patel, “Chapter 4: The Von Neumann Model.” | ||
| - | === Suggested readings (Lecture 11): === | ||
| - | * {{preliminary_discussion_burks1946.pdf | A.W. Burks, H.H. Goldstein, J. von Neumann, “Preliminary Discussion of the Logical Design of an Electronic Computing Instrument,” The Origins of Digital Computers, 1946}} | ||
| - | === Mentioned in Lecture 11: === | ||
| - | * {{Dennis.pdf|Dennis and Misunas, “A preliminary architecture for a basic data-flow processor,” ISCA 1974.}} | ||
| - | * {{gurd-cacm85-prototype.pdf|Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985.}} | ||
| - | * D. Harris and S. Harris, “Chapter 5.2.1" | ||
| ===== Lecture 12 (15.04 Thu.) ===== | ===== Lecture 12 (15.04 Thu.) ===== | ||
readings.1625488376.txt.gz · Last modified: 2021/07/05 14:32 by jispark
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