Combinational Logic: “Y.N. Patt and S.J. Patel” Chapter 3 until 3.3 + “D. Harris and S. Harris” Chapter 2
Sequential Logic: “Y.N. Patt and S.J. Patel” Chapter 3.4 until end + “D. Harris and S. Harris” Chapter 3 in full
Hardware Description Languages and Verilog: “D. Harris and S. Harris” Chapter 4 in full
Timing and Verification: “D. Harris and S. Harris” Chapters 2.9 and 3.5 + (start Chapter 5)
“Y.N. Patt and S.J. Patel” Chapters 1-3 + “D. Harris and S. Harris” Chapters 1-4
Von Neumann Model, LC-3, and MIPS: “Y.N. Patt and S.J. Patel”, Chapters 4, 5 + “D. Harris and S. Harris”, Chapter 6 + “Y.N. Patt and S.J. Patel”, Appendices A and C (ISA and microarchitecture of LC-3) + “D. Harris and S. Harris”, Appendix B (MIPS instructions)
Programming: “Y.N. Patt and S.J. Patel”, Chapter 6