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Buzzwords

Buzzwords are terms that are mentioned during lecture which are particularly important to understand thoroughly. This page tracks the buzzwords for each of the lectures and can be used as a reference for finding gaps in your understanding of course material.

Lecture 1 (24.02 Thu.)

  • Algorithm
  • Program
  • Language
  • System software
  • SW/HW Interface
  • Microarchitecture
  • Logic
  • Transistors
  • Computer Architecture
  • Wafer-scale
  • Transistor
  • Hamming code
  • Transformation Hierarchy (Computing Stack)
  • Logic gates
  • Accelerator
  • Instruction Set Architecture
  • Workload
  • Computing Platform
  • Machine Learning (?)
  • Redundancy
  • Specialization
  • Genome Analysis
  • Processing-in-Memory
  • Data Movement
  • ImageNet
  • Tensor Cores
  • Cutting-edge
  • Software/Hardware Co-Design
  • DRAM
  • FPGA
  • Reconfigurable Architecture
  • Instructions
  • Performance
  • Efficiency
  • Systolic Arrays
  • Reliability Safety Security Privacy
  • RowHammer

Lecture 2a (25.02 Fri.)

  • Metrics
  • Tradeoffs
  • Principled design
  • Debug
  • Critical Thinking
  • Machine Learning
  • Combinational Logic
  • Sequential Logic

Lecture 2b (25.02 Fri.)

  • Transformation hierarchy
  • Hamming distance
  • Error correcting codes (ECC)
  • Levels of transformation
  • Abstraction levels
  • Accelerator
  • Meltdown & Spectre
  • Rambleed
  • DeepHammer
  • Microarchitecture
  • Security attacks
  • Hardware security vulnerabilities
  • Speculative execution
  • Microarchitecture
  • Instruction Set Architecture (ISA)
  • Cache
  • Timing side channel
  • Rowhammer
  • RDMA
  • Deep Neural Networks
  • Refresh rate
  • Disturbance errors
  • DRAM module
  • DRAM cell
  • Bit flips
  • Page table entry (PTE)
  • PARA: Probabilistic Adjacent Row Activation
  • Byzantine failures
  • Maslow’s Hierarchy
  • Reliability
  • DDR4
  • Technology node

Lecture 3a (03.03 Thu.)

  • Mysteries in Computer Architecture
  • Hardware security vulnerabilities
  • Disturbance errors
  • Bit flips
  • Rowhammer
  • PARA: Probabilistic Adjacent Row Activation
  • BlockHammer
  • Maslow’s Hierarchy
  • Reliability, Safety, Security
  • DRAM Refresh
  • Retention Time Profile of DRAM
  • Manufacturing Process Variation
  • RAIDR: Eliminating Unnecessary DRAM Refreshes
  • Bloom Filters (not explained in detail)

Lecture 3b (03.03 Thu.)

  • Lab Sessions
  • Grading Policy
  • Deadlines for Lab Exercises and Lab Reports
  • The Transformation Hierarchy
  • Hardware Prototyping
  • Debugging a Hardware Implementation
  • Hardware Description Languages (HDL)
  • Hardware Design Flow
  • Computer-Aided Design (CAD)
  • Project Brainwave
  • Amazon EC2 F1
  • FPGA-based DNA Sequencing
  • FPGA-based DRAM Characterization
  • SoftMC
  • FPGA-based Flash Memory Characterization
  • Basys 3 FPGA Board
  • High Level Summary of Labs
  • Seven Segment Display
  • Finite State Machines
  • ALU: Arithmetic and Logic Unit
  • Testing and Simulation
  • Assembly Language
  • FPGA: Field Programmable Gate Array
  • FPGA Building Blocks
  • Look-Up Tables (LUT)
  • Switches
  • Multiplexers
  • Xilinx Zynq Ultrascale+
  • FPGA Design Flow
  • Xilinx Vivado
  • Verilog code
  • Logic Synthesis
  • Placement and Routing

Lecture 4 (04.03 Fri.)

  • Computation, Communication, Storage/Memory
  • General-Purpose Microprocessors
  • FPGAs
  • ASICs
  • GPUs
  • Transistor
  • MOS transistor
  • n-type/p-type MOS transistor
  • nMOS
  • pMOS
  • Logic gates
  • Complementary MOS (CMOS)
  • CMOS NOT gate
  • CMOS NAND gate
  • Truth table
  • CMOS AND gate
  • CMOS NOR gate
  • Pull-up, pull-down
  • Common logic gates
  • Moore’s Law
  • Combinational logic circuits
  • Boolean equations
  • Boolean algebra
  • Boolean Algebra Axioms
  • DeMorgan’s Law

Lecture 5 (10.03 Thu.)

  • Transistors
  • Logic Gates
  • Apple M1
  • Apple M1 Ultra
  • DRAM
  • FPGA
  • ASIC
  • GPU
  • EUV
  • DeMorgan's Law
  • Sum of Products Form (SOP)
  • Product of Sums (POS)
  • Decoder
  • Multiplexer
  • Selector
  • Full Adder
  • Programmable Logic Array (PLA)
  • Comparator
  • Arithmetic Logic Unit (ALU)
  • Tri-State Buffer
  • Karnaugh Maps
  • Binary Coded Decimal (BCD)

Lecture 6 (11.03 Fri.)

  • Sequential circuit
  • Storage element
  • Cross-coupled inverters
  • Stable state
  • Metastable state
  • SRAM (static random access memory)
  • Bitline
  • Wordline
  • Latches
  • Flip-flops
  • DRAM (dynamic random access memory)
  • Flash memory
  • Hard disk
  • Tape
  • R-S (reset-set) latch
  • Gated D-latch
  • Memory array
  • Address
  • Addressability
  • Address space
  • Multiplexer
  • Selector
  • Decoder
  • Memory-based lookup table
  • State
  • State diagram
  • Asynchronous/synchronous state changes
  • Clock
  • Finite state machine (FSM)
  • Next state logic
  • State register
  • Output logic
  • D flip-flops
  • Positive edge
  • Edge-triggered state element
  • Moore FSM
  • Mealy FSM
  • Transition diagram
  • FSM output table
  • Fully encoded
  • 1-hot encoded
  • Output encoded
  • State transition diagram
  • Reset state
  • LC-3 processor

Lecture 7 (17.03 Thu.)

  • Hardware Description Language (HDL)
  • Verilog
  • VHDL
  • Specialized languages
  • Combinational logic
  • Sequential logic
  • Parallelism
  • Hardware synthesis
  • Hardware simulation
  • Hierarchical design
  • Leaf cell
  • Cell library
  • Verilog module
  • Structural (gate-level) design
  • Behavioral design
  • Reduction operation
  • Ternary operator
  • Schematic
  • Invalid value
  • Floating signal
  • Netlist
  • Semi-custom design
  • Full-custom design
  • Timing
  • Storage element
  • Clock
  • Verilog always block
  • Sensitivity list
  • Reset signal
  • Asynchronous/synchronous reset
  • Metastability
  • Glitch
  • Rising/falling edge
  • Blocking/non-blocking assignments

Lecture 8 (18.03 Fri.)

Circuit Timing

  • Combinational Circuit Timing
  • Contamination Delay, Propagation Delay
  • Critical Path, Shortest Path
  • Output Glitches
  • Sequential Circuit Timing
  • Timing Constraints
  • Setup Time, Hold Time, Aperture Time
  • Metastability
  • Contamination Delay clock-to-q
  • Propagation Delay clock-to-q
  • Design Performance
  • Clock Skew
  • Clock Network

Circuit Verification

  • Logic Synthesis Tools
  • Timing Verification Tools
  • Design Rule Checks
  • Functional Verification
  • Simple Testbench
  • Self-Checking Testbench
  • Testvectors
  • Automatic Testbench

Lecture 9 (24.03 Fri.)

  • von Neumann model
  • LC-3
  • MIPS
  • Assembly
  • Programming
  • Single-cycle
  • Microarchitecture
  • Multi-cycle
  • Processing
  • Memory
  • HW/SW Interface
  • Instruction Set Architecture
  • Inputs/Outputs
  • Control Unit
  • Address space
  • Byte-Addressable Memory
  • Big-Endian
  • Little-Endian
  • Register File
  • Fetch
  • Decode
  • Execute
  • opcode
  • ALU

Lecture 10a (25.03 Fri.)

  • von Neumann model
  • LC-3
  • MIPS
  • Stored Program Computer
  • Assembly
  • The Instruction Set Architecture (ISA)
  • Opcodes
  • Data Types
  • Registers
  • Immediate
  • Literal
  • Program Counter (PC)
  • Offset
  • Operate Instructions
  • Data Path
  • Data Movement Instructions
  • Addressing Modes
  • Register Set
  • Instruction Set
  • Opcode
  • Jumps
  • PC-Relative Addressing Mode
  • Indirect Addressing Mode
  • Base+Offset Addressing Mode
  • Immediate Addressing Mode
  • Control Flow Instructions
  • Condition Codes
  • Conditional Branches
  • Complex Instructions
  • Simple Instructions
  • x86, VAX, SIMD ISAs, VLIW ISAs, PowerPC, RISC ISAs
  • Binary Coded Decimal
  • Semantic Gap

Lecture 10b (25.03 Fri.)

  • von Neumann model
  • LC-3
  • MIPS
  • Assembly Programming
  • The Instruction Set Architecture (ISA)
  • Sequential Construct
  • Conditional Construct
  • Iterative Construct
  • TRAP Instruction
  • Debugging
  • Conditional Statements
  • Loops
  • If Statement
  • While, For Loops
  • Arrays in MIPS
  • Function Calls
  • Stack

Lecture 11 (31.03 Thu.)

  • Microarchitecture
  • Von Neumann Machine
  • Instruction Set Architecture (ISA)
  • Stored program computer
  • Sequential instruction processing
  • Unified memory
  • Instruction pointer
  • Data flow model
  • Data flow dependence
  • Instruction pointer
  • Data flow node
  • Control-flow execution order
  • Data-flow execution order
  • Pipeline
  • Instruction and data caches
  • General purpose registers
  • Virtual ISA
  • Single-cycle microarchitecture
  • Multi-cycle microarchitecture
  • Critical path
  • Control unit
  • Instruction Fetch
  • Instruction Decode
  • Functional units
  • Datapath
  • Control logic
  • Cycles Per Instruction (CPI)
  • Register file
  • Arithmetic Logic Unit (ALU)
  • Store writeback
  • Arithmetic and Logical instructions

Lecture 12 (01.04 Fri.)

  • Load Word Datapath
  • Store Word Datapath
  • Non-Control-Flow Instruction Datapath
  • Unconditional Jump Datapath
  • Conditional Branch Datapath
  • Control Signals
  • Single-Cycle Microarchitecture
  • Multi-Cycle Microarchitecture

Lecture 13 (07.04 Thu.)

  • Pipelining
  • Control & data dependence handling
  • State maintenance and recovery
  • Multi-cycle design
  • Concurrency
  • Instruction throughput
  • Assembly line processing
  • Pipeline stages
  • Uniformly partitionable suboperations
  • The instruction processing cycle
  • Instruction fetch (IF)
  • Instruction decode and Register operand fetch (ID/RF)
  • Execute/Evaluate memory address (EX/AG)
  • Memory operand fetch (MEM)
  • Store/writeback result (WB)
  • Pipeline registers
  • Control points
  • Control signals
  • Pipeline stalls
  • Resource contention
  • Dependences (data/control)
  • Long-latency (multi-cycle) operations
  • Data dependences
  • Flow dependence
  • Output dependence
  • Anti dependence
  • Data dependence handling
  • Interlocking
  • Scoreboarding
  • Combinational dependence check logic
  • Data forwarding/bypassing
  • RAW dependence handling
  • Stalling hardware

Lecture 14 (08.04 Fri.)

  • Pipelining
  • Control & data dependence handling
  • Stalling
  • Stalling hardware
  • Hazard unit
  • Data forwarding
  • Control dependence
  • Branch prediction
  • Branch misprediction penalty
  • Instructions flushing
  • Early branch resolution
  • Pipelined performance
  • SPECINT2017 benchmark
  • Average CPI
  • Software-based interlocking
  • Hardware-based interlocking
  • Pipeline bubbles
  • Software-based instruction scheduling
  • Hardware-based instruction scheduling
  • Static / dynamic scheduling
  • Variable-length operation latency
  • Fine-grained multithreading
  • Dependency checking
  • GPU
  • Multithreading

Lecture 15 (14.04 Thu.)

  • Execute stage
  • Multi-cycle execution
  • Pipeline
  • Execution/functional units
  • Von Neumann architecture
  • Sequential semantics
  • Exception
  • Interrupt
  • Divide by zero
  • Overflow
  • Page fault
  • Exception handling
  • Instruction retirement
  • Precise state
  • Flushing instructions
  • Exception handling routine
  • Software debugging
  • Traps
  • Exception program counter
  • Exception handling routine
  • Instruction latency
  • Reorder buffer (ROB)
  • Circular queue
  • Out-of-order execution
  • Instruction reordering
  • Architectural state
  • Retired/Committed instruction
  • Pipeline stall
  • Register file
  • Content-addressable memory (CAM)
  • Producer and consumer instruction
  • Register renaming
  • Indirection
  • Architectural/Physical register
  • True/Output/Anti dependences

Lecture 16a (28.04 Thu.)

  • Out-of-Order Execution
  • Data Dependence
  • In-order Execution
  • Dispatch Stalls
  • Tomasulo’s Algorithm
  • IBM 360/91
  • Dataflow
  • Precise Exceptions
  • Intel Pentium Pro
  • Intel Pentium 4
  • Alpha 21264
  • MIPS R10000
  • IBM POWER4
  • IBM POWER5
  • AMD Zen2
  • Apple M1 FireStorm

Lecture 16b (28.04 Thu.)

  • Out-of-Order Execution
  • Loads and Stores
  • Registers
  • Memory Dependence Handling
  • Memory address
  • Memory disambiguation problem
  • Handling of Store-Load Dependences
  • Store-Load Forwarding

Lecture 17a (29.04 Fri.)

  • Out-of-Order Execution
  • Restricted Dataflow
  • Reorder buffer
  • Physical Register File
  • Register map
  • Renaming
  • Reservation stations
  • Tag broadcast
  • Wakeup and select
  • Instruction window
  • Tomasulo's algorithm
  • Register Alias Table
  • Dataflow graph
  • Instruction Level Parallelism
  • Irregular parallelism
  • Superscalar execution

Lecture 17b (29.04 Fri.)

  • Branch prediction
  • Control dependence handling
  • Branch delay slot
  • Fine-grained multithreading
  • Predicated execution
  • Multipath execution
  • Misprediction penalty
  • Pipeline flush
  • Branch Target Buffer (BTB)
  • Global Branch History
  • Static/Dynamic branch prediction
  • Last Time Predictor
  • Tow-Bit Counter Based Prediction (also called bimodal prediction)
  • Saturating counter
  • Global branch correlation
  • Two Level Global History Branch Prediction
  • Two-Level Gshare Branch Predictor
  • Local Branch Correlation
  • Two-Level Local History Branch Predictor
  • Hybrid Branch Predictors
  • Alpha 21264 Tournament Predictor
  • Loop branch detector and predictor
  • Perceptron branch predictor
  • Hybrid history length based predictor
  • TAGE Branch Predictor
  • Patten History Table (PHT)
  • Delayed Branching

Lecture 18 (05.05 Thu.)

  • Static branch prediction
  • Compiler-directed prediction
  • Profile based prediction
  • Program based prediction
  • Programmer based prediction
  • Taken vs. not-taken branch
  • Heuristics
  • Pragmas
  • Dynamic/run time branch prediction
  • Last time predictor
  • Branch history table (BHT)
  • Counter based prediction, hysteresis, bimodal prediction
  • Global branch correlation
  • Local branch correlation
  • Global branch predictor
  • Global branch history register
  • Pattern history table
  • Local branch predictor
  • Local history
  • Per-branch history register
  • Hybrid branch predictors
  • Predictor warmup time
  • Loop branch detector and predictor
  • Perceptron branch predictor
  • Hybrid history-length based predictor, TAGE
  • Prediction confidence

Lecture 19a (06.05 Fri.)

  • Very Long Instruction Word (VLIW)
  • Superscalar
  • Lock-Step Execution
  • RISC
  • Commercial VLIW Machines
  • VLIW Tradeoffs
  • Superblock
  • ISA translation

Lecture 19b (06.05 Fri.)

  • Systolic Arrays
  • Processing Element (PE)
  • Regular array of PEs
  • Convolutional Neural Network
  • Matrix Multiplication
  • LeNet-5, AlexNet, GoogLeNet, ResNet
  • ImageNet
  • Two-Dimensional Systolic Arrays
  • Programmability in Systolic Arrays
  • Staged execution
  • Pipeline-Parallel (Pipelined) Programs
  • Google's TPU

Lecture 19c (06.05 Fri.)

  • Decoupled Access-Execute (DAE)
  • Instruction stream
  • ISA-visible queue
  • Loop unrolling

Lecture 20 (12.05 Fri.)

  • Array Processor
  • Vector Processor
  • Lane
  • Vector Registers
  • Vector Mask
  • Flynn
  • Amdahl's law
  • SIMD
  • SISD
  • MIMD
  • MISD

Lecture 21 (13.05 Fri.)

  • SIMD
  • Intel MMX
  • MIMD
  • Fine-grained multithreading
  • Control and data dependences
  • Thread context
  • Programming model
  • Hardware execution model
  • Instruction-level parallelism
  • Vectorized code
  • Warp/Wavefront
  • Shader core
  • Scalar pipeline
  • GPU kernels
  • CUDA
  • Streaming multiprocessors
  • Bank-level parallelism
  • Branch divergence
  • Dynamic warp formation
  • Systolic arrays
  • FLOPs
  • Precision

Lecture 22 (19.05 Thu.)

  • Memory System, Memory Bottleneck
  • Application Perspective
  • Processing in Memory (PIM) accelerators
  • Data Movement Energy
  • Reliability, Security Perspectives
  • Programmer’s View
  • Virtual, Physical Memory
  • Latches/FlipFlops, SRAM, DRAM, Flash
  • DRAM vs SRAM
  • Memory Organization
  • Interleaving/Banking
  • Channel, Rank, Bank, Subarray, Mat
  • Chip Select
  • DRAM technology
  • SRAM technology
  • Memory Bank Organization
  • Phase Change Memory (PCM)
  • Charge memory vs Resistive memories

Lecture 23 (20.05 Fri.)

  • DRAM vs SRAM
  • Phase Change Memory (PCM)
  • DRAM vs PCM
  • Memory hierarchy
  • Memory locality
  • Temporal locality
  • Spatial locality
  • Caching basics
  • Caching in a pipelined design
  • Hierarchical latency analysis
  • Access latency and miss penalty
  • Hit-rate, miss-rate
  • Direct-mapped cache
  • Set associativity
  • Full associativity
  • Eviction/replacement policy

Lecture 26 (03.06 Fri.)

  • Virtual memory
  • Physical memory
  • Infinite capacity
  • Relocation
  • Protection and isolation
  • Sharing
  • Linear address
  • Real address
  • Page table
  • OS-managed lookup table
  • Address translation
  • Physical frame
  • Demand paging
  • Placing, replacement, granularity of management, write policy
  • Page
  • Page size
  • Page offset
  • Page fault
  • Virtual page number (VPN)
  • Physical page number (PPN)
  • Virtual address
  • Physical address
  • Physical page number (physical frame number)
  • Page replacement policy
  • Page dirty bit
  • Page table base register (PTBR)
  • Page fault
  • Multi-level (hierarchical) page table
  • Translation Lookaside Buffer (TLB)
  • Memory Management Unit (MMU)
  • Page Table Entry
  • Tag store
  • Page hit, page fault
  • OS trap handler
  • Direct Memory Access (DMA)
  • Interrupt processor
  • Access protection bits
  • Access protection exception
  • Privilege levels
  • DRAM disturbance errors
  • RowHammer
buzzword.txt · Last modified: 2022/07/18 09:17 by firtinac