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Readings

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Lecture 1 (24.02 Thu.)

Suggested readings (Lecture 1):

Mentioned in Lecture 1:

Lecture 2a (25.02 Fri.)

Reading assignments (Lecture 2a):

  • D. Harris and S. Harris, “Chapter 1: From Zero to One. Digital Design and Computer Architecture.”
  • Y.N. Patt and S.J. Patel, “Chapter 1: Welcome Aboard. Introduction to Computing Systems.”
  • Y.N. Patt and S.J. Patel, “Chapter 2: Bits, Data Types, and Operations. Introduction to Computing Systems.”

Lecture 2b (25.02 Fri.)

Suggested readings (Lecture 2b):

Mentioned in Lecture 2b:

Lecture 3a (03.03 Thu.)

Suggested readings (Lecture 3a):

Mentioned in Lecture 3a:

Lecture 3b (03.03 Thu.)

Mentioned in Lecture 3b:

Lecture 4 (04.03 Fri.)

Required video lecture assignments (Lecture 4):

Reading assignments (Lecture 4):

  • D. Harris and S. Harris, “Chapter 2: Combinational Logic Design.”
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” until 3.3.
  • D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog” until 4.3 and 4.5.
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” from 3.4 until the end.
  • D. Harris and S. Harris, “Chapter 3: Sequential Logic” in full.

Suggested readings (Lecture 4):

Mentioned in Lecture 4:

Lecture 5 (10.03 Thu.)

Required video lecture assignments (Lecture 5):

Reading assignments (Lecture 5):

  • D. Harris and S. Harris, “Chapter 2: Combinational Logic Design.”
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” until 3.3.
  • D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog” until 4.3 and 4.5.
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” from 3.4 until the end.
  • D. Harris and S. Harris, “Chapter 3: Sequential Logic” in full.

Suggested readings (Lecture 5):

  • D. Harris and S. Harris, “Section 5.1, Chapter 5: Digital Building Blocks.”
  • D. Harris and S. Harris, “Section 5.2, Chapter 5: Digital Building Blocks.”
  • D. Harris and S. Harris, “Section 5.6.1, Chapter 5: Digital Building Blocks.”
  • D. Harris and S. Harris, “Section 2.7, Chapter 2: Combinational Logic Design.”

Mentioned in Lecture 5:

Lecture 6 (11.03 Fri.)

Required video lecture assignments (Lecture 6):

Reading assignments (Lecture 6):

Combinational Logic

  • D. Harris and S. Harris, Chapter 2.7
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” until 3.3

Sequential Logic

  • D. Harris and S. Harris, “Chapter 2: Combinational Logic Design.”
  • Y.N. Patt and S.J. Patel, “Chapter 3: Digital Logic Structures” from 3.4 until the end.

Hardware Description Languages and Verilog

  • D. Harris and S. Harris, “Chapter 3: Sequential Logic” in full.
  • D. Harris and S. Harris, “Chapter 4: Hardware Description Languages and Verilog” in full

Timing and Verification

  • D. Harris and S. Harris, Chapters 2.9 and 3.5 + (start “Chapter 5: Digital Building Blocks”)

Mentioned in Lecture 6:

Lecture 8 (17.03 Fri.)

Required video lecture assignments (Lecture 8):

Reading assignments (Lecture 8):

Von Neumann Model, LC-3, and MIPS

  • Y.N. Patt and S.J. Patel, Chapters 4-5
  • D. Harris and S. Harris, Chapter 6
  • Y.N. Patt and S.J. Patel, Appendix A and C (ISA and microarchitecture of LC-3)
  • D. Harris and S. Harris, Appendix B (MIPS instructions)

Programming

  • Y.N. Patt and S.J. Patel, Chapter 6

Recommended: Digital Building Blocks

  • D. Harris and S. Harris, Chapter 5

Mentioned in Lecture 8:

Lecture 9 (24.03 Thu.)

Required video lecture assignments (Lecture 9):

Reading assignments (Lecture 9):

  • D. Harris and S. Harris, “Chapter 6” (until 6.5)
  • D. Harris and S. Harris, “Chapters 2.9 and 3.5: Timing and Verification.”
  • D. Harris and S. Harris, “Chapter 5: Digital Building Blocks.” (especially 5.1, 5.2, 5.4, 5.5)
  • Y.N. Patt and S.J. Patel “Chapters 4,5” (Full)
  • Y.N. Patt and S.J. Patel “Chapter 6” (Full)
  • Y.N. Patt and S.J. Patel, “Appendices A and C” (ISA and microarchitecture of LC-3)

Lecture 10a (25.03 Fri.)

Required video lecture assignments (Lecture 10a):

Reading assignments (Lecture 10a):

  • D. Harris and S. Harris, “Chapter 6” (until 6.5)
  • Y.N. Patt and S.J. Patel “Chapters 4,5” (Full)
  • Y.N. Patt and S.J. Patel “Chapter 6” (Full)
  • Y.N. Patt and S.J. Patel, “Appendices A and C” (ISA and microarchitecture of LC-3)
  • D. Harris and S. Harris, “Appendix B” (MIPS instructions)

Suggested readings (Lecture 10a):

  • D. Harris and S. Harris, “Chapter 5” (especially 5.1,5.2,5.4,5.5)

Lecture 10b (25.03 Fri.)

Required video lecture assignments (Lecture 10b):

Reading assignments (Lecture 10b):

Mentioned in Lecture 10b:

Lecture 11 (31.03 Thu.)

Required video lecture assignments (Lecture 11):

Reading assignments (Lecture 11):

  • D. Harris and S. Harris, “Chapter 7.1–7.3”
  • Y.N. Patt and S.J. Patel, “Appendices A and C”
  • D. Harris and S. Harris, “Chapter 7.4” (Multi-cycle microarchitecture)
  • D. Harris and S. Harris, “Chapters 7.5” (Pipelining)
  • D. Harris and S. Harris, “Chapters 7.7, 7.8.1–7.8.3” (Pipelining Issues)

Suggested readings (Lecture 11):

Lecture 12 (01.04 Fri.)

Required video lecture assignments (Lecture 12):

Reading assignments (Lecture 12):

  • D. Harris and S. Harris, “Chapter 7.1–7.3”
  • Y.N. Patt and S.J. Patel, “Appendices A and C”
  • D. Harris and S. Harris, “Chapter 7.4” (Multi-cycle microarchitecture)
  • D. Harris and S. Harris, “Chapters 7.5” (Pipelining)
  • D. Harris and S. Harris, “Chapters 7.7, 7.8.1–7.8.3” (Pipelining Issues)

Suggested readings (Lecture 12):

Lecture 13 (07.04 Thu.)

Reading assignments (Lecture 13):

  • D. Harris and S. Harris, “Chapter 7.5”
  • D. Harris and S. Harris, “Chapters 7.8.1–7.8.3”

Suggested readings (Lecture 13):

Lecture 14 (08.04 Apr.)

Reading assignments (Lecture 14a):

Suggested readings (Lecture 14)

Mentioned in Lecture 14:

Lecture 15 (14.04 Apr.)

Reading assignments:

  • D. Harris and S. Harris, “Chapter 7.5”
  • D. Harris and S. Harris, “Chapter 7.7”
  • D. Harris and S. Harris, “​Chapter 7.8.1 - 7.8.3”​

Suggested readings

Mentioned in Lecture:

Lecture 16 (28.04 Apr.)

Reading assignments:

Suggested readings

Mentioned in Lecture:

Lecture 17a (29.04 Apr.)

Reading assignments:

  • Smith and Sohi, “The Microarchitecture of Superscalar Processors,” Proceedings of the IEEE, 1995
  • D. Harris and S. Harris, “​Chapter 7.8 - 7.9”​
  • McFarling, “Combining Branch Predictors,” DEC WRL Technical Report, 1993.

Suggested readings

  • Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 1999.
  • Dennis and Misunas, “A preliminary architecture for a basic data-flow processor,” ISCA 1974.
  • Gurd et al., “The Manchester prototype dataflow computer,” CACM 1985.
  • More detailed Lecture Video & Slides on DataFlow:
    Lecture Video
    Slides
  • Lecture on Load-Store Handling in OoO
    Lecture Video

Mentioned in Lecture:

  • Smith and Sohi, “The Microarchitecture of Superscalar Processors,” Proc. IEEE, Dec. 1995.
  • Mutlu+, “Runahead Execution,” HPCA 2003.
  • Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro, March-April 1999.
  • Yeager, “The MIPS R10000 Superscalar Microprocessor,” IEEE Micro, April 1996
  • Tendler et al.,“POWER4 system microarchitecture,” IBM J R&D, 2002.
  • Kalla et al., “IBM Power5 Chip: A Dual-Core Multithreaded Processor,” IEEE Micro 2004.

Lecture 18 (05.05 Thu.)

Reading assignments:

Suggested readings

Mentioned in Lecture:

Lecture 19a (06.05 Fri.)

Mentioned in Lecture:

Lecture 19b (06.05 Fri.)

Reading assignments (Lecture 19b):

Suggested readings (Lecture 19b):

Mentioned in Lecture 19b:

Lecture 19c (06.05 Fri.)

Mentioned in Lecture 19c:

Lecture 20 (12.05 Thu.)

Reading Assignments (Lecture 20)

Suggested Readings (Lecture 20)

Mentioned Readings (Lecture 20)

Lecture 21 (13.05 Fri.)

Reading assignments:

  • Lindholm et al., “NVIDIA Tesla: A Unified Graphics and Computing Architecture,” IEEE Micro 2008.

Suggested readings

  • Peleg and Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro 1996.

Mentioned in Lecture:

  • Mike Flynn, “Very High-Speed Computing Systems,” Proc. of IEEE, 1966
  • Fisher, “Very Long Instruction Word architectures and the ELI-512,” ISCA 1983.
  • Amdahl, “Validity of the single processor approach to achieving large scale computing capabilities,” AFIPS 1967.
  • Peleg and Weiser, “MMX Technology Extension to the Intel Architecture,” IEEE Micro, 1996.
  • Rocki et al., “Fast stencil-code computation on a wafer-scale processor.” SC 2020.
  • Thornton, “Parallel Operation in the Control Data 6600,” AFIPS 1964.
  • Smith, “A pipelined, shared resource MIMD computer,” ICPP 1978.
  • Narasiman et al., “Improving GPU Performance via Large Warps and Two-Level Warp Scheduling,” MICRO 2011.
  • NVIDIA, “NVIDIA GeForce GTX 200 GPU. Architectural Overview. White Paper,” 2008.
  • NVIDIA, “NVIDIA Tesla V100 GPU Architecture. White Paper,” 2017.
  • M. A. Raihan, N. Goli and T. M. Aamodt, “Modeling Deep Learning Accelerator Enabled GPUs,” ISPASS 2019.

Lecture 22 (19.05 Thu.)

Reading assignments:

  • D. Harris and S. Harris, “​Chapter 8.1 - 8.3”​
  • Y.N. Patt and S.J. Patel, “Chapter 3.5”
  • Kim & Mutlu, “Memory Systems,” Computing Handbook, 2014.

Suggested readings

  • Wilkes, “Slave Memories and Dynamic Storage Allocation,” IEEE Trans. On Electronic Computers, 1965.

Mentioned in Lecture:

  • Burks et al., “Preliminary discussion of the logical design of an electronic computing instrument,” 1946.
  • Senol Cali et al., “Nanopore Sequencing Technology and Tools for Genome Assembly: Computational Analysis of the Current State, Bottlenecks and Future Directions,” Briefings in Bioinformatics, 2018.
  • Alser et al., “Accelerating Genome Analysis: A Primer on an Ongoing Journey” IEEE Micro, August 2020.
  • Singh et al., “FPGA-based Near-Memory Acceleration of Modern Data-Intensive Applications”, IEEE Micro, 2021.
  • Senol Cali et al., “GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis”, MICRO, 2020.
  • Mansouri Ghiasi et al., “GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis”, ASPLOS, 2022.
  • Senol Cali et al., “SeGraM: A Universal Hardware Accelerator for Genomic Sequence-to-Graph and Sequence-to-Sequence Mapping”, ISCA, 2022.
  • Mutlu et al., “Runahead Execution: An Effective Alternative to Large Instruction Windows”, IEEE Micro, 2003.
  • Kanev et al., “Profiling a Warehouse-Scale Computer,” ISCA, 2015.
  • Gray and Mutlu, “‘It’s the memory, stupid’: A conversation with Onur Mutlu”, HiPEAC Newsletter, 2018.
  • Han et al., “EIE: Efficient Inference Engine on Compressed Deep Neural Network,” ISCA, 2016.
  • Boroumand et al., “Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks”, ASPLOS, 2018.
  • Mutlu, “Memory-Centric Computing”, ESWEEK, 2021.
  • Meza et al., “Revisiting Memory Errors in Large-Scale Production Data Centers,” DSN, 2015.
  • Kim et al., “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors”, ISCA, 2014.
  • Seaborn et al., “Exploiting the DRAM rowhammer bug to gain kernel privileges”, 2015
  • Mutlu and Kim, “RowHammer: A Retrospective”, TCAD Special Issue on Top Picks in Hardware and Embedded Security, 2019.
  • Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA, 2012.
  • Lee et al., “Decoupled Direct Memory Access,” PACT, 2015.
  • Lee et al., “Architecting Phase Change Memory as a Scalable DRAM Alternative,” ISCA, 2009.
  • Cai et al., “Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid State Drives,” Proc. IEEE, 2017.
  • Mutlu, “Memory-Centric Computing Systems”, IEDM, 2020.

Lecture 23 (20.05 Fri.)

Reading assignments (Lecture 23):

Suggested readings (Lecture 23):

Mentioned in Lecture 23:

Lecture 26 (03.06 Fri.)

Reading assignments (Lecture 26):

  • D. Harris and S. Harris, “Chapter 8.4”
  • Y. Kim and O. Mutlu, “Memory Systems,” Computing Handbook, 2014.

Suggested readings (Lecture 26):

  • Bruce Jacob and Trevor Mudge, “Virtual Memory: Issues of Implementation,” IEEE Computer, 1998.
  • Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, and Onur Mutlu, “The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework,” In ISCA, 2020.

Mentioned in Lecture 26:

readings.txt · Last modified: 2022/07/14 14:59 by nadigr