Welcome to the wiki for Memory Systems. This course material is from Onur Mutlu's lectures October 8-12, 2018 at Technion

The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy efficiency, performance, and reliability significantly more costly with conventional techniques. In fact, recent reliability issues with DRAM, such as the RowHammer problem, are already threatening system security and predictability. We are at the challenging intersection where issues in memory reliability and performance are tightly coupled with not only system cost and energy efficiency but also system security.

In this course, we first provide a comprehensive overview of memory systems, taking an approach that covers both fundamentals and recent research. We first introduce fundamental principles and ideas, covering DRAM and emerging memory technologies as well as many architectural concepts and ideas related to memory organization, memory control, processing-in-memory, and memory latency / energy / bandwidth / reliability / security / QoS. We discuss major challenges facing modern memory systems (and the computing platforms we currently design around the memory system) in the presence of greatly increasing demand for data and its fast analysis. We examine some promising research and design directions to overcome these challenges. On the research-related part of course (sprinkled across topical lectures), we discuss the following key research topics in detail, focusing on both open problems and potential solution directions:

1. Fundamental issues in memory reliability and security and how to enable fundamentally secure, reliable, safe architectures
2. Enabling data-centric and hence fundamentally energy-efficient architectures that are capable of performing computation near data
3. Reducing both latency and energy consumption by tackling the fixed-latency/energy mindset
4. Enabling emerging memory technologies
5. Enabling predictable and QoS-aware memory systems
6. Research challenges and opportunities in enabling emerging NVM (non-volatile memory) technologies
7. Scaling NAND flash memory and SSDs (solid state drives) into the future

Course Syllabus

Many of these topics are based on the following graduate-level course at ETH Zurich: https://safari.ethz.ch/architecture/fall2017/doku.php?id=schedule.

Prerequisites: A rigorous computer architecture and digital design course similar to: https://safari.ethz.ch/digitaltechnik/spring2018/doku.php?id=schedule