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====== Memory Systems: Fundamentals, | ====== Memory Systems: Fundamentals, | ||
- | Welcome to the wiki for Memory Systems. | + | Welcome to the wiki for Memory Systems. |
=====Course Information===== | =====Course Information===== | ||
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====Outline==== | ====Outline==== | ||
- | In this course, we first provide a comprehensive overview of memory systems, taking an approach that covers both fundamentals and recent research. We will first introduce fundamental principles and ideas, covering DRAM and emerging memory technologies as well as many architectural concepts and ideas related to memory organization, | + | In this course, we first provide a comprehensive overview of memory systems, taking an approach that covers both fundamentals and recent research. We first introduce fundamental principles and ideas, covering DRAM and emerging memory technologies as well as many architectural concepts and ideas related to memory organization, |
On the research-related part of course (sprinkled across topical lectures), we discuss the following key research topics in detail, focusing on both open problems and potential solution directions: | On the research-related part of course (sprinkled across topical lectures), we discuss the following key research topics in detail, focusing on both open problems and potential solution directions: | ||
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- Scaling NAND flash memory and SSDs (solid state drives) into the future | - Scaling NAND flash memory and SSDs (solid state drives) into the future | ||
- | + | {{ :memory_systems-syllabus_with_schedule.pdf | Course Syllabus }} | |
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- | ====Topics==== | + | |
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- | The following are topics the course will discuss in varying detail: | + | |
- | | + | |
- | - Cache Management and Memory Parallelism | + | |
- | - Main Memory and DRAM Fundamentals | + | |
- | - DRAM Operation, Memory Control & Memory Latency | + | |
- | - Low-Latency DRAM and Processing In Memory | + | |
- | - Emerging Memory Technologies | + | |
- | - Memory Interference and Quality of Service | + | |
- | - Multi-Core Cache Management | + | |
- | - Latency Tolerance and Prefetching | + | |
- | - Multiprocessors, | + | |
- | - Interconnects: | + | |
- | - NAND Flash Memory (if time permits) | + | |
- | - Potpourri of Recent Research Papers | + | |
Many of these topics are based on the following graduate-level course at ETH Zurich: https:// | Many of these topics are based on the following graduate-level course at ETH Zurich: https:// | ||
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https:// | https:// | ||
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- | ==== Lectures (Slides and Videos) ==== | + | |
- | - a) Memory Importance and Trends, b) Course Logistics, c) Main Memory and DRAM Basics (Taught on Oct 8th)\\ Lecture Slides {{ : | + | |
- | - a) Memory Scaling: Reliability & Security, b) Flash Memory Reliability & Security, c) DRAM Refresh (Taught on Oct 9th)\\ Lecture Slides {{ : | + | |
- | - Processing-in-Memory (Taught on Oct 9th)\\ Lecture Slides {{ : | + | |
- | - Low-Latency Memory (Taught on Oct 10th)\\ Lecture Slides {{ : | + | |
- | - Emerging Memory Technologies (Taught on Oct 10th)\\ Lecture Slides {{ : | + | |
- | - Memory Interference and QoS (Taught on Oct 10th and Oct 11th)\\ Lecture Slides {{ : | + | |
- | - Interconnects (Taught on Oct 11th and Oct 12th)\\ Lecture Slides {{ : | + | |
- | - Asymmetric Multi-Core\\ Lecture Slides {{ : | + | |
- | + | ||
- | **Links to previous courses: | + | |
- | [[https:// | + | |
- | [[https:// | + |
start.1545778815.txt.gz · Last modified: 2019/02/12 16:34 (external edit)