ACACES Memory Systems Course -- July 2018

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====== Extended Reading List ======

Most of the readings we will touch on are provided in the course slides. You can find most readings here https://people.inf.ethz.ch/omutlu/projects.htm

As time permits, other covered or mentioned readings will be provided on this page. 

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<h3>Readings for Topic 1 (Memory Trends and Basics)</h3>

<h4>DRAM Basics</h4>

<ul>


<p><li> 
     Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/salp-dram_isca12.pdf">"A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM"</a></b><br> <i>Proceedings of the <a href="http://isca2012.ittc.ku.edu/">39th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Portland, OR, June 2012.
     <a href="https://people.inf.ethz.ch/omutlu/pub/kim_isca12_talk.pptx">Slides (pptx)</a> 
     <br> </li>

<p><li>
     Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/tldram_hpca13.pdf">"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture"</a></b> <br> <i>Proceedings of the <a href="http://www.cs.utah.edu/~lizhang/HPCA19/">19th International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Shenzhen, China, February 2013.      <a href="https://people.inf.ethz.ch/omutlu/pub/lee_hpca13_talk.pptx">Slides (pptx)</a> 
</li>

<p><li>Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Samira Khan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/smla_high-bandwidth-3d-stacked-memory_taco16.pdf">"Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost"</a></b> <br>
     <i><a href="http://taco.acm.org/">ACM Transactions on Architecture and Code Optimization</a> (<b>TACO</b>)</i>, Vol. 12,January 2016. <br>Presented at the <a href="https://www.hipeac.net/2016/prague/">11th HiPEAC Conference<a>, Prague, Czech Republic, January 2016. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/smla_high-bandwidth-3d-stacked-memory_ghose_hipeac16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/smla_high-bandwidth-3d-stacked-memory_ghose_hipeac16-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://github.com/CMU-SAFARI/SMLA">Source Code</a>]

<p><li>Donghyuk Lee, Lavanya Subramanian, Rachata Ausavarungnirun, Jongmoo Choi, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/decoupled-dma_pact15.pdf">"Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM"</a></b><br>
     <i>Proceedings of the <a href="https://sites.google.com/a/lbl.gov/pact2015/">24th International Conference on Parallel Architectures and Compilation Techniques</a> (<b>PACT</b>)</i>, San Francisco, CA, USA, October 2015.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/decoupled-dma_donghyuk_pact15-talk.pptx">Slides (pptx)</a>  <a href="https://people.inf.ethz.ch/omutlu/pub/decoupled-dma_donghyuk_pact15-talk.pdf">(pdf)</a>]      <br> </li>

</ul>

<h4>DRAM Refresh</h4>

<ul>

<p><li> 
     Jamie Liu, Ben Jaiyen, Richard Veras, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf">"RAIDR: Retention-Aware Intelligent DRAM Refresh"</a></b><br>
     <i>Proceedings of the <a href="http://isca2012.ittc.ku.edu/">39th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Portland, OR, June 2012.
     <a href="https://people.inf.ethz.ch/omutlu/pub/liu_isca12_talk.pdf">Slides (pdf)</a> 
     <br> </li>

<p><li> 
     Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-retention-time-characterization_isca13.pdf">"An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms"</a></b><br>
     <i>Proceedings of the <a href="http://isca2013.eew.technion.ac.il/">40th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Tel-Aviv, Israel, June 2013.
     <a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_isca13_talk.ppt">Slides (ppt)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_isca13_talk.pdf">Slides (pdf)</a> <br> 
     </li>

<p><li>
     Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-access-refresh-parallelization_hpca14.pdf">"Improving DRAM Performance by Parallelizing Refreshes with Accesses"</a></b> <br>
     <i>Proceedings of the <a href="http://hpca20.ece.ufl.edu/">20th International Symposium on High-Performance Computer 
     Architecture</a> (<b>HPCA</b>)</i>, Orlando, FL, February 2014.      [<a href="https://people.inf.ethz.ch/omutlu/pub/dram-access-refresh-parallelization_hpca14-summary.pdf">Summary</a>]    [<a href="https://people.inf.ethz.ch/omutlu/pub/dram-access-refresh-parallelization_chang_hpca14-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dram-access-refresh-parallelization_chang_hpca14-talk.pdf">(pdf)</a>] 
</li>

<p><li> 
     Minesh Patel, Jeremie S. Kim, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17.pdf">"The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions"</a></b><br>
     <i>Proceedings of the <a href="http://isca17.ece.utoronto.ca/doku.php">44th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Toronto, Canada, June 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-talk.pdf">(pdf)</a>]
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-lightning-talk.pdf">(pdf)</a>]
     <br></li>


</ul>



<h4>Simulating Memory</h4>

<ul>

<p><li>
     Yoongu Kim, Weikun Yang, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf">"Ramulator: A Fast and Extensible DRAM Simulator"</a></b><br>
     <i><a href="http://www.computer.org/web/cal">IEEE Computer Architecture Letters</a> (<b>CAL</b>)</i>, March 2015. 
     <br>[<a href="https://github.com/CMU-SAFARI/ramulator">Source Code</a>]
  </li>

<p><li>
     Arash Tavakkol, Juan Gomez-Luna, Mohammad Sadrosadati, Saugata Ghose, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18.pdf">"MQSim: A Framework for Enabling Realistic Studies of Modern Multi-Queue SSD Devices"</a></b> <br>
     <i>Proceedings of the <a href="https://www.usenix.org/conference/fast18">16th USENIX Conference on File and Storage Technologies</a> (<b>FAST</b>)</i>, Oakland, CA, USA, February 2018.      
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/MQSim-SSD-simulation-framework_fast18-talk.pptx">Slides (pptx)</a> <a href="pub/MQSim-SSD-simulation-framework_fast18-talk.pdf">(pdf)</a>]<!--[<a href="pub/softMC_hpca17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="pub/softMC_hpca17-lightning-talk.pdf">(pdf)</a>] -->
     <br>[<a href="https://github.com/CMU-SAFARI/MQSim">Source Code</a>]
</li>

</ul>



<h4>Memory Control</h4>

<ul>

 <p><li 
     ><u>Onur
     Mutlu</u> and Thomas Moscibroda, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/stfm_micro07.pdf">&quot;Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors&quot;</a></b> <br>
     <i>Proceedings of the <a
     href="http://www.microarch.org/micro40/">40th International Symposium on
     Microarchitecture</a> (<b>MICRO</b>)</i>, pages 146-158, Chicago, IL, December 2007. [<a href="https://people.inf.ethz.ch/omutlu/pub/stfm_micro07-summary.pdf">Summary</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_micro07_talk.ppt">Slides (ppt)</a>] </li>

<p><li 
     ><u>Onur Mutlu</u> and Thomas Moscibroda, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/parbs_isca08.pdf">&quot;Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems&quot;</a></b><br>
     <i>Proceedings of the <a href="http://isca2008.cs.princeton.edu/">35th International Symposium on
     Computer Architecture</a> (<b>ISCA</b>)</i>, pages 63-74, Beijing, China, June 2008. [<a href="https://people.inf.ethz.ch/omutlu/pub/parbs_isca08-summary.pdf">Summary</a>] [<a href="pub/mutlu_isca08_talk.ppt">Slides (ppt)</a>]<br>
     <b><i><font color="red"'>One of the 12 computer architecture papers
     of 2008 selected as Top Picks by IEEE Micro.</font></i></b> </li>

<p><li 
     >Engin Ipek, <u>Onur Mutlu</u>, Jos&#233; F. Mart&#237;nez, and Rich Caruana, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/rlmc_isca08.pdf">&quot;Self Optimizing Memory Controllers: A Reinforcement Learning Approach&quot;</a></b><br>
     <i>Proceedings of the <a href="http://isca2008.cs.princeton.edu/">35th International Symposium on
     Computer Architecture</a> (<b>ISCA</b>)</i>, pages 39-50, Beijing, China, June 2008. <a href="https://people.inf.ethz.ch/omutlu/pub/ipek_isca08_talk.pptx">Slides (pptx)</a> </li>


<p><li 
     >Yoongu Kim, Michael Papamichael, <u>Onur Mutlu</u>, and Mor Harchol-Balter,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/tcm_micro10.pdf">"Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior"</a></b> <br>
     <i>Proceedings of the <a href="http://www.microarch.org/micro43/">43rd International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, pages 65-76, Atlanta, GA, December 2010. 
     <a href="https://people.inf.ethz.ch/omutlu/pub/kim_micro10_talk.pptx">Slides (pptx)</a> <a href="pub/kim_micro10_talk.pdf">(pdf)</a> 
     <br><b><i><font color="red"'>One of the 11 computer architecture papers
     of 2010 selected as Top Picks by IEEE Micro.</font></i></b> </li>


<p><li>Lavanya Subramanian, Donghyuk Lee, Vivek Seshadri, Harsha Rastogi, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/bliss-memory-scheduler_ieee-tpds16.pdf">"BLISS: Balancing Performance, Fairness and Complexity in Memory Access Scheduling"</a></b><br> 
     <i><a href="http://www.computer.org/web/tpds/">IEEE Transactions on Parallel and Distributed Systems</a> (<b>TPDS</b>)</i>, to appear in 2016.
     <a href="http://arxiv.org/pdf/1504.00390.pdf">arXiv.org version</a>, April 2015. <br>
     <a href="https://people.inf.ethz.ch/omutlu/pub/bliss-memory-scheduler_cmu-safari-tr15.pdf">An earlier version</a> as <a href="http://www.ece.cmu.edu/~safari/tr.html"><i>SAFARI Technical Report</i></a>, TR-SAFARI-2015-004, Carnegie Mellon University, March 2015.
     <br>[<a href="https://github.com/CMU-SAFARI/MemSchedSim">Source Code</a>]</li>

<p><li>Hiroyuki Usui, Lavanya Subramanian, Kevin Kai-Wei Chang, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dash_deadline-aware-heterogeneous-memory-scheduler_taco16.pdf">"DASH: Deadline-Aware High-Performance Memory Scheduler for Heterogeneous Systems with Hardware Accelerators"</a></b> <br>
     <i><a href="http://taco.acm.org/">ACM Transactions on Architecture and Code Optimization</a> (<b>TACO</b>)</i>, Vol. 12, January 2016. 
     <br>Presented at the <a href="https://www.hipeac.net/2016/prague/">11th HiPEAC Conference<a>, Prague, Czech Republic, January 2016. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/dash_deadline-aware-heterogeneous-memory-scheduler_usui_hipeac16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dash_deadline-aware-heterogeneous-memory-scheduler_usui_hipeac16-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://github.com/CMU-SAFARI/HWASim">Source Code</a>]
</li>

<p><li 
     >Eiman Ebrahimi, Chang Joo Lee, <u>Onur Mutlu</u>, and Yale N. Patt,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/fairness-via-throttling_acm_tocs12.pdf">"Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems"</a></b> <br>
     <i><a href="http://tocs.acm.org/">ACM Transactions on Computer Systems</a> (<b>TOCS</b>)</i>, April 2012.
     <br> <a href="http://hps.ece.utexas.edu/pub/TR-HPS-2012-001.pdf">A previous version</a> as HPS Technical Report, TR-HPS-2012-001, February 2012. </li>
     </li>

<p><li>Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Khan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/application-slowdown-model_micro15.pdf">
     "The Application Slowdown Model: Quantifying and Controlling the Impact of Inter-Application Interference at Shared Caches and Main Memory"</a></b><br> 
     <i>Proceedings of the <a href="http://www.microarch.org/micro48/">48th International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, Waikiki, Hawaii, USA, December 2015. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/application-slowdown-model_lavanya_micro15-talk.pptx">Slides (pptx)</a> <a href="pub/application-slowdown-model_lavanya_micro15-talk.pdf">(pdf)</a>] [<a href="pub/application-slowdown-model_lavanya_micro15-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/application-slowdown-model_lavanya_micro15-lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/application-slowdown-model_lavanya_micro15-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/application-slowdown-model_lavanya_micro15-poster.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/ASMSim">Source Code</a>]
     <br> </li>


<p><li 
     >Chang Joo Lee, Veynu Narasiman, Eiman Ebrahimi, <u>Onur Mutlu</u>, and Yale N. Patt, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-aware-caches-TR-HPS-2010-002.pdf">"DRAM-Aware Last-Level Cache
     Writeback: Reducing Write-Caused Interference in Memory
     Systems"</a></b><br> HPS Technical Report, TR-HPS-2010-002,
     April 2010. </li>

</ul>



<h3>Readings for Topic 2 (Memory Reliability and Security)</h3>

<h4>RowHammer</h4>

<ul>

<p><li> 
     Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf"-->"Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors"</a></b><br>
     <i>Proceedings of the <a href="http://cag.engr.uconn.edu/isca2014/">41st International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Minneapolis, MN, June 2014.
    <br> [<a href="https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_kim_talk_isca14.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_kim_talk_isca14.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_kim_lightning-talk_isca14.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_kim_lightning-talk_isca14.pdf">(pdf)</a>] [<a href="https://github.com/CMU-SAFARI/rowhammer">Source Code and Data</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/rowhammer.pptx">RowHammer Summary Slides (pptx)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/rowhammer-summary.pdf">RowHammer Summary</a>]
    <br> [<a href="http://www.zdnet.com/article/flipping-dram-bits-maliciously/">Coverage on ZDNet 1</a>] [<a href="http://www.zdnet.com/article/rowhammer-dram-flaw-could-be-widespread-says-google/">Coverage on ZDNet 2</a>] [<a href="http://www.memtest86.com/troubleshooting.htm">MemTest86 Hammer Test</a>] [<a href="https://groups.google.com/forum/#!forum/rowhammer-discuss">RowHammer Discussion Group</a>] [<a href="https://twitter.com/hashtag/rowhammer?f=realtime">Discussion on Twitter</a>]
     <br>      </li>


<p><li>
     <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/rowhammer-and-other-memory-issues_date17.pdf">"The RowHammer Problem and Other Issues We May Face as Memory Becomes Denser"</a></b> <br>
     <i>Invited Paper in Proceedings of the <a href="http://www.date-conference.com/">Design, Automation, and Test in Europe Conference</a> (<b>DATE</b>)</i>, Lausanne, Switzerland, March 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/onur-Rowhammer-Memory-Security_date17-invited-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/onur-Rowhammer-Memory-Security_date17-invited-talk.pdf">(pdf)</a>] 
     </li>

</ul>



<h4>Large-Scale Memory Reliability Studies</h4>


<ul>

<p><li>
     Justin Meza, Qiang Wu, Sanjeev Kumar, and <u>Onur Mutlu</u>,<br> 
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/memory-errors-at-facebook_dsn15.pdf">"Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field"</a></b> <br>
     <i>Proceedings of the <a href="http://2015.dsn.org/">45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks</a> (<b>DSN</b>)</i>, Rio de Janeiro, Brazil, June 2015.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/memory-errors-at-facebook_dsn15-talk.pptx">Slides (pptx)</a> <a href="pub/memory-errors-at-facebook_dsn15-talk.pdf">(pdf)</a>]  [<a href="https://www.ece.cmu.edu/~safari/tools/memerr/index.html">DRAM Error Model</a>]

<p><li>
     Justin Meza, Qiang Wu, Sanjeev Kumar, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf">"A Large-Scale Study of Flash Memory Errors in the Field"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2015/"> ACM International Conference on Measurement and Modeling of Computer Systems</a> 
     (<b>SIGMETRICS</b>)</i>, Portland, OR, June 2015.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15-talk.pdf">(pdf)</a>] [<a href="http://www.zdnet.com/article/facebooks-ssd-experience/">Coverage at ZDNet</a>] [<a href="http://www.theregister.co.uk/2015/06/22/facebook_reveals_ssd_failure_rate_trough/">Coverage on The Register</a>] [<a href="http://www.techspot.com/news/61090-researchers-publish-first-large-scale-field-ssd-reliability.html">Coverage on TechSpot</a>] [<a href="http://techreport.com/news/28519/facebook-ssd-reliability-study-shows-early-burnouts">Coverage on The Tech Report</a>]
  <!--a href="pub/neighbor-assisted-error-correction-in-flash_cai_sigmetrics14-talk.ppt">Slides (ppt)</a> <a href="pub/neighbor-assisted-error-correction-in-flash_cai_sigmetrics14-talk.pdf">(pdf)</a> <a href="pub/neighbor-assisted-error-correction-in-flash_cai_sigmetrics14-poster.ppt">Poster (ppt)</a-->
</li>

</ul>


<h4>DRAM Testing Infrastructure</h4>

<ul>

<p><li>
     Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf">"SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies"</a></b> <br>
     <i>Proceedings of the <a href="https://hpca2017.org/">23rd International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Austin, TX, USA, February 2017.      
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-lightning-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://github.com/CMU-SAFARI/SoftMC">Source Code</a>]
</li>

</ul>


<h4>DRAM Refresh and Data Retention</h4>

<ul>

<p><li> 
     Jamie Liu, Ben Jaiyen, Richard Veras, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf">"RAIDR: Retention-Aware Intelligent DRAM Refresh"</a></b><br>
     <i>Proceedings of the <a href="http://isca2012.ittc.ku.edu/">39th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Portland, OR, June 2012.
     <a href="https://people.inf.ethz.ch/omutlu/pub/liu_isca12_talk.pdf">Slides (pdf)</a> 
     <br> </li>

<p><li> 
     Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-retention-time-characterization_isca13.pdf">"An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms"</a></b><br>
     <i>Proceedings of the <a href="http://isca2013.eew.technion.ac.il/">40th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Tel-Aviv, Israel, June 2013.
     <a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_isca13_talk.ppt">Slides (ppt)</a> <a href="pub/mutlu_isca13_talk.pdf">Slides (pdf)</a> <br> 
     </li>


<p><li>
     Samira Khan, Donghyuk Lee, Yoongu Kim, Alaa Alameldeen, Chris Wilkerson, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf">"The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2014/"> ACM International Conference on Measurement and Modeling of Computer Systems 
     </a> (<b>SIGMETRICS</b>)</i>, Austin, TX, June 2014.  [<a href="https://people.inf.ethz.ch/omutlu/pub/error-mitigation-for-intermittent-dram-failures_khan_sigmetrics14-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/error-mitigation-for-intermittent-dram-failures_khan_sigmetrics14-talk.pdf">(pdf)</a>]
     [<a href="https://people.inf.ethz.ch/omutlu/pub/error-mitigation-for-intermittent-dram-failures_khan_sigmetrics14-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/error-mitigation-for-intermittent-dram-failures_khan_sigmetrics14-poster.pdf">(pdf)</a>] [<a href="http://www.ece.cmu.edu/~safari/tools/dram-sigmetrics2014-fulldata.html">Full data sets</a>]
</li>

<p><li>
     Moinuddin Qureshi, Dae Hyun Kim, Samira Khan, Prashant Nair, and <u>Onur Mutlu</u>,<br> 
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/avatar-dram-refresh_dsn15.pdf">"AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems"</a></b> <br>
     <i>Proceedings of the <a href="http://2015.dsn.org/">45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks</a> (<b>DSN</b>)</i>, Rio de Janeiro, Brazil, June 2015.  
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/avatar-dram-refresh_dsn15-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/avatar-dram-refresh_dsn15-talk.pdf">(pdf)</a>]
<!--[<a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_luo_dsn14-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_luo_dsn14-talk.pdf">(pdf)</a>] [<a href="http://www.zdnet.com/how-good-does-memory-need-to-be-7000031853/">Coverage on ZDNet</a>]-->

<p><li>
     Samira Khan, Donghyuk Lee, and <u>Onur Mutlu</u>,<br> 
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/parbor-efficient-system-level-test-for-DRAM-failures_dsn16.pdf">"PARBOR: An Efficient System-Level Technique to Detect Data-Dependent Failures in DRAM"</a></b> <br>
     <i>Proceedings of the <a href="http://2015.dsn.org/">45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks</a> (<b>DSN</b>)</i>, Toulouse, France, June 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/parbor-efficient-system-level-test-for-DRAM-failures_khan_dsn16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/parbor-efficient-system-level-test-for-DRAM-failures_khan_dsn16-talk.pdf">(pdf)</a>]


<p><li>
     Samira Khan, Chris Wilkerson, Zhe Wang, Alaa R. Alameldeen, Donghyuk Lee, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17.pdf">
     "Detecting and Mitigating Data-Dependent DRAM Failures by Exploiting Current Memory Content"</a></b><br> 
     <i>Proceedings of the <a href="http://www.microarch.org/micro50/">50th International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, Boston, MA, USA, October 2017. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/MEMCON-system-level-data-dependent-DRAM-failure-detection-mitigation_micro17-poster.pdf">(pdf)</a>]
     <!--br>[<a href="https://github.com/CMU-SAFARI/ASMSim">Source Code</a>]-->
     <br> </li>

<p><li> 
     Minesh Patel, Jeremie S. Kim, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17.pdf">"The Reach Profiler (REAPER): Enabling the Mitigation of DRAM Retention Failures via Profiling at Aggressive Conditions"</a></b><br>
     <i>Proceedings of the <a href="http://isca17.ece.utoronto.ca/doku.php">44th International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Toronto, Canada, June 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-talk.pptx">Slides (pptx)</a> <a href="pub/reaper-dram-retention-profiling-lpddr4_isca17-talk.pdf">(pdf)</a>]
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/reaper-dram-retention-profiling-lpddr4_isca17-lightning-talk.pdf">(pdf)</a>]
     <br></li>

</ul>

<h4>Heterogeneous Reiability Memory</h4>

<ul>

<p><li>
     Yixin Luo, Sriram Govindan, Bikash Sharma, Mark Santaniello, Justin Meza, Aman Kansal, Jie Liu, Badriddine Khessib, Kushagra Vaid, and <u>Onur Mutlu</u>,<br> 
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf">"Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost via Heterogeneous-Reliability Memory"</a></b> <br>
     <i>Proceedings of the <a href="http://2014.dsn.org/">44th Annual IEEE/IFIP International Conference on Dependable Systems and Networks
     </a> (<b>DSN</b>)</i>, Atlanta, GA, June 2014.  [<a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory_dsn14-summary.pdf">Summary</a>]  [<a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_luo_dsn14-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/heterogeneous-reliability-memory-for-data-centers_luo_dsn14-talk.pdf">(pdf)</a>] [<a href="http://www.zdnet.com/how-good-does-memory-need-to-be-7000031853/">Coverage on ZDNet</a>]

</ul>



<h3>Readings for Topic 3 (In-Memory Computation)</h3>

<h4>Runahead Execution</h4>

<ul>

 <p><li 
     ><u>Onur Mutlu</u>, Jared
     Stark, Chris Wilkerson, and Yale N. Patt, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_ieee_micro03.pdf">&quot;Runahead Execution: An
     Effective Alternative to Large Instruction Windows&quot;</a></b><br>
     <i><a href="http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261383">IEEE
     Micro, Special Issue: Micro's Top Picks from Microarchitecture Conferences</a>
     (<b>MICRO TOP PICKS</b>)</i>, Vol. 23, No. 6, pages 20-25,
     November/December 2003. </li>
 <p><li 
     ><u>Onur Mutlu</u>, Jared
     Stark, Chris Wilkerson, and Yale N. Patt, <br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/mutlu_hpca03.pdf">&quot;Runahead Execution: An Alternative
     to Very Large Instruction Windows for Out-of-order Processors&quot;</a></b><br>
     <i>Proceedings of the <a href="http://www.cs.arizona.edu/hpca9/">9th
     International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>,
     pages 129-140, Anaheim, CA, February 2003. <a
     href="https://people.inf.ethz.ch/omutlu/pub/mutlu_hpca03_talk.pdf">Slides (pdf)</a> <br>
     <b><i><span style='color:red'>One of the 15 computer architecture papers
     of 2003 selected as Top Picks by IEEE Micro.</span></i></b> </li>

</ul>


<h4>Data Movement Cost in Mobile Devices</h4>

<ul>

<p><li>
     Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf">"Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks"</a></b> <br>
     <i>Proceedings of the <a href="https://www.asplos2018.org/">23rd International Conference on Architectural Support for Programming Languages and Operating Systems</a> (<b>ASPLOS</b>)</i>, Williamsburg, VA, USA, March 2018.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-poster.pdf">(pdf)</a>]
     <!--br>[<a href="https://github.com/CMU-SAFARI/SoftMC">Source Code</a>]-->

</ul>


<h4>In-DRAM Computation and Data Movement</h4>

<ul>

<p><li>Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, <u>Onur Mutlu</u>, Michael A. Kozuch, Phillip B. Gibbons, and Todd C. Mowry,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/rowclone_micro13.pdf">
     "RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization"</a></b><br> 
     <i>Proceedings of the <a href="http://www.microarch.org/micro46/">46th International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, Davis, CA, December 2013. 
     [<a href="https://people.inf.ethz.ch/omutlu/pub/rowclone_seshadri_micro13-talk.pptx">Slides (pptx)</a> <a href="pub/rowclone_seshadri_micro13-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/rowclone_seshadri_micro13_lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/rowclone_seshadri_micro13_lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/rowclone_seshadri_micro13-poster.pptx">Poster (pptx)</a> <a href="pub/rowclone_seshadri_micro13-poster.pdf">(pdf)</a>]
     <br> </li>

<p><li>
     Vivek Seshadri, Donghyuk Lee, Thomas Mullins, Hasan Hassan, Amirali Boroumand, Jeremie Kim, Michael A. Kozuch, <u>Onur Mutlu</u>, Phillip B. Gibbons, and Todd C. Mowry,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf">
     "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology"</a></b><br> 
     <i>Proceedings of the <a href="http://www.microarch.org/micro50/">50th International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, Boston, MA, USA, October 2017. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17-poster.pdf">(pdf)</a>]
     <!--br>[<a href="https://github.com/CMU-SAFARI/ASMSim">Source Code</a>]-->
     <br> </li>

</ul>


<h4>Processing in 3D-Stacked Memory and Memory Controllers</h4>

<ul>

<p><li> 
     Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, <u>Onur Mutlu</u>, and Kiyoung Choi,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf">"A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing"</a></b><br>
     <i>Proceedings of the <a href="http://www.ece.cmu.edu/calcm/isca2015/">42nd International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Portland, OR, June 2015.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15-talk.pdf">Slides (pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15-lightning-talk.pdf">Lightning Session Slides (pdf)</a>]
     <br><b><i><font color="red"'>Top Picks Honorable Mention by IEEE Micro.</font></i></b> 
     <!-- [<a href="https://people.inf.ethz.ch/omutlu/pub/dirty-block-index_seshadri_talk_isca14.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dirty-block-index_seshadri_talk_isca14.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/dirty-block-index_seshadri_lightning-talk_isca14.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dirty-block-index_seshadri_lightning-talk_isca14.pdf">(pdf)</a>] -->
     <br></li>

<p><li> 
     Kevin Hsieh, Eiman Ebrahimi, Gwangsun Kim, Niladrish Chatterjee, Mike O'Connor, Nandita Vijaykumar, <u>Onur Mutlu</u>, and Stephen W. Keckler,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_isca16.pdf">"Transparent Offloading and Mapping (TOM): Enabling Programmer-Transparent Near-Data Processing in GPU Systems"</a></b><br>
     <i>Proceedings of the <a href="http://isca2016.eecs.umich.edu/">43rd International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Seoul, South Korea, June 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-lightning-talk.pdf">(pdf)</a>] 
     <br></li>

<p><li>Ashutosh Pattnaik, Xulong Tang, Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, <u>Onur Mutlu</u>, and Chita R. Das,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/scheduling-for-GPU-processing-in-memory_pact16.pdf">"Scheduling Techniques for GPU Architectures with Processing-In-Memory Capabilities"</a></b><br>
     <i>Proceedings of the <a href="http://pactconf.org/">25th International Conference on Parallel Architectures and Compilation Techniques</a> (<b>PACT</b>)</i>, Haifa, Israel, September 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/scheduling-for-GPU-processing-in-memory_pattnaik_pact16-talk.pptx">Slides (pptx)</a>  <a href="https://people.inf.ethz.ch/omutlu/pub/scheduling-for-GPU-processing-in-memory_pattnaik_pact16-talk.pdf">(pdf)</a>]
     <!-- <br>[<a href="https://github.com/CMU-SAFARI/MeDiC">Source Code</a>] -->
     <br> </li>

<p><li>Kevin Hsieh, Samira Khan, Nandita Vijaykumar, Kevin K. Chang, Amirali Boroumand, Saugata Ghose, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/in-memory-pointer-chasing-accelerator_iccd16.pdf">"Accelerating Pointer Chasing in 3D-Stacked Memory: Challenges, Mechanisms, Evaluation"</a></b><br> 
     <i> Proceedings of the <a href="http://www.iccd-conf.com/">34th IEEE International Conference on Computer Design</a> (<b>ICCD</b>)</i>, Phoenix, AZ, USA, October 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/in-memory-pointer-chasing-accelerator_hsieh_iccd16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/in-memory-pointer-chasing-accelerator_hsieh_iccd16-talk.pdf">(pdf)</a>] 
     <!-- <br> <a href="pub/bliss-memory-scheduler_cmu-safari-tr15.pdf">An extended version</a> as SAFARI Technical Report, TR-SAFARI-2015-004, Carnegie Mellon University, March 2015.-->
     <br>[<a href="https://github.com/CMU-SAFARI/IMPICA">Source Code</a>]
     <br> </li>

<p><li> 
     Milad Hashemi, Khubaib, Eiman Ebrahimi, <u>Onur Mutlu</u>, and Yale N. Patt,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/enhanced-memory-controller-for-dependent-loads_isca16.pdf">"Accelerating Dependent Cache Misses with an Enhanced Memory Controller"</a></b><br>
     <i>Proceedings of the <a href="http://isca2016.eecs.umich.edu/">43rd International Symposium on Computer Architecture</a> (<b>ISCA</b>)</i>, Seoul, South Korea, June 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/enhanced-memory-controller-for-dependent-loads_milad_isca16-talk.pptx">Slides (pptx)</a> <a href="pub/enhanced-memory-controller-for-dependent-loads_milad_isca16-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/enhanced-memory-controller-for-dependent-loads_milad_isca16-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/enhanced-memory-controller-for-dependent-loads_milad_isca16-lightning-talk.pdf">(pdf)</a>] 
     <!-- [<a href="pub/dirty-block-index_seshadri_talk_isca14.pptx">Slides (pptx)</a> <a href="pub/dirty-block-index_seshadri_talk_isca14.pdf">(pdf)</a>] [<a href="pub/dirty-block-index_seshadri_lightning-talk_isca14.pptx">Lightning Session Slides (pptx)</a> <a href="pub/dirty-block-index_seshadri_lightning-talk_isca14.pdf">(pdf)</a>] -->
     <br></li>

<p><li>Milad Hashemi, <u>Onur Mutlu</u>, and Yale N. Patt,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/continuous-runahead-engine_micro16.pdf">
     "Continuous Runahead: Transparent Hardware Acceleration for Memory Intensive Workloads"</a></b><br> 
     <i>Proceedings of the <a href="http://www.microarch.org/micro49/">49th International Symposium on Microarchitecture</a> (<b>MICRO</b>)</i>, Taipei, Taiwan, October 2016. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/continuous-runahead-engine_micro16-talk.pptx">Slides (pptx)</a> <a href="pub/continuous-runahead-engine_micro16-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/continuous-runahead-engine_micro16-lightning-session-talk.pdf">Lightning Session Slides (pdf)</a><!--a href="pub/application-slowdown-model_lavanya_micro15-lightning-talk.pdf">(pdf)</a-->] [<a href="pub/continuous-runahead-engine_micro16-poster.pptx">Poster (pptx)</a> <a href="pub/continuous-runahead-engine_micro16-poster.pdf">(pdf)</a>]
     <br><b><i><font color="red">One of the six papers nominated for the Best Paper Award by the Program Committee.</font></i></b> 
     <!--br>[<a href="https://github.com/CMU-SAFARI/ASMSim">Source Code</a>]-->
     <br> </li>

</ul>

<h4>Coherence Support</h4>

<ul>

<p><li>
     Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/LazyPIM-coherence-for-processing-in-memory_ieee-cal16.pdf">"LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory"</a></b><br>
     <i><a href="http://www.computer.org/web/cal">IEEE Computer Architecture Letters</a> (<b>CAL</b>)</i>, June 2016. 
     <!--br>[<a href="https://github.com/CMU-SAFARI/ramulator">Source Code</a>]-->
  </li>

</ul>

<h4>Data Structures for In-Memory Computation</h4>

<ul>


<p><li> 
     Zhiyu Liu, Irina Calciu, Maurice Herlihy, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/concurrent-data-structures-for-PIM_spaa17.pdf">"Concurrent Data Structures for Near-Memory Computing"</a></b><br>
     <i>Proceedings of the <a href="https://spaa.acm.org/">29th ACM Symposium on Parallelism in Algorithms and Architectures</a> (<b>SPAA</b>)</i>, Washington, DC, USA, July 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/concurrent-data-structures-for-PIM_spaa17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/concurrent-data-structures-for-PIM_spaa17-talk.pdf">(pdf)</a>]
     <!--br>[<a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/TOM-programmer-transparent-GPU-near-data-processing_kevinhsieh_isca16-lightning-talk.pdf">(pdf)</a>] -->
     <br></li>

</ul>

<h4>Simulation Infrastructures for In-Memory Computation</h4>

<ul>

<p><li>
     Yoongu Kim, Weikun Yang, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf">"Ramulator: A Fast and Extensible DRAM Simulator"</a></b><br>
     <i><a href="http://www.computer.org/web/cal">IEEE Computer Architecture Letters</a> (<b>CAL</b>)</i>, March 2015. 
     <br>[<a href="https://github.com/CMU-SAFARI/ramulator">Source Code</a>]
  </li>

<p><li>
     Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf">"SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies"</a></b> <br>
     <i>Proceedings of the <a href="https://hpca2017.org/">23rd International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Austin, TX, USA, February 2017.      
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-talk.pptx">Slides (pptx)</a> <a href="pub/softMC_hpca17-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17-lightning-talk.pdf">(pdf)</a>] 
     <br>[<a href="https://github.com/CMU-SAFARI/SoftMC">Source Code</a>]
</li>

</ul>


<h4>New Applications and Use Cases for In-Memory Computation</h4> 

<ul>

<p><li> 
     Jeremie S. Kim, Damla Senol Cali, Hongyi Xin, Donghyuk Lee, Saugata Ghose, Mohammed Alser, Hasan Hassan, Oguz Ergin, Can Alkan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://arxiv.org/pdf/1711.01177.pdf">"GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies"</a></b></br>
     <i><a href="http://www.biomedcentral.com/bmcgenomics/"><b>BMC Genomics</b></a></i>, 2018. <!--a href="http://www.biomedcentral.com/content/pdf/1471-2164-14-S1-S13.pdf">PDF article</a><br-->
     <br><i>Proceedings of the <a href="http://apbc2018.bio.keio.ac.jp/">16th Asia Pacific Bioinformatics Conference</a> (<b>APBC</b>)</i>, Yokohama, Japan, January 2018. 
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/GRIM-filter-DNA-pre-alignment-in-memory_apbc18-talk.pptx">Slides (pptx)</a> <a href="GRIM-filter-DNA-pre-alignment-in-memory_apbc18-talk.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/GRIM">Source Code</a>]
     <br><a href="https://arxiv.org/pdf/1711.01177.pdf">arxiv.org Version (pdf)</a>
</li>

<p><li>
     Amirali Boroumand, Saugata Ghose, Youngsok Kim, Rachata Ausavarungnirun, Eric Shiu, Rahul Thakur, Daehyun Kim, Aki Kuusela, Allan Knies, Parthasarathy Ranganathan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf">"Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks"</a></b> <br>
     <i>Proceedings of the <a href="https://www.asplos2018.org/">23rd International Conference on Architectural Support for Programming Languages and Operating Systems</a> (<b>ASPLOS</b>)</i>, Williamsburg, VA, USA, March 2018.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-lightning-talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-poster.pptx">Poster (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18-poster.pdf">(pdf)</a>]
     <!--br>[<a href="https://github.com/CMU-SAFARI/SoftMC">Source Code</a>]-->
</li>

</ul>

<h4>Enabling Adoption of In-Memory Computation</h4>

<ul>

<p><li>
     Saugata Ghose, Kevin Hsieh, Amirali Boroumand, Rachata Ausavarungnirun, and <u>Onur Mutlu</u>,<br>
     <b><a href="">"Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions"</a></b> <br>
     <i>Invited Book Chapter</i>, to appear in 2018.
     <br>[<a href="https://arxiv.org/pdf/1802.00320.pdf">Preliminary arxiv.org version</a>]
     <!--br>[<a href="https://people.inf.ethz.ch/omutlu/pub/onur-Rowhammer-Memory-Security_date17-invited-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/onur-Rowhammer-Memory-Security_date17-invited-talk.pdf">(pdf)</a>]--> 
     </li>

</ul>




<h3>Readings for Topic 4 (Low-Latency Memory)</h3>

<h4>Tackling the Fixed-Latency Mindset</h4>

<ul>

<p><li>
     Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/adaptive-latency-dram_hpca15.pdf">"Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case"</a></b> <br>
     <i>Proceedings of the <a href="http://darksilicon.org/hpca/">21st International Symposium on High-Performance Computer 
     Architecture</a> (<b>HPCA</b>)</i>, Bay Area, CA, February 2015.      
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/adaptive-latency-dram_donghyuk_hpca15-talk.pptx">Slides (pptx)</a> <a href="pub/adaptive-latency-dram_donghyuk_hpca15-talk.pdf">(pdf)</a>] [<a href="http://www.ece.cmu.edu/~safari/tools/aldram-hpca2015-fulldata.html">Full data sets</a>]
</li>

<p><li>
     Kevin Chang, Abhijith Kashyap, Hasan Hassan, Samira Khan, Kevin Hsieh, Donghyuk Lee, Saugata Ghose, Gennady Pekhimenko, Tianshi Li, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/understanding-latency-variation-in-DRAM-chips_sigmetrics16.pdf">"Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2016/"> ACM International Conference on Measurement and Modeling of Computer Systems</a> 
     (<b>SIGMETRICS</b>)</i>, Antibes Juan-Les-Pins, France, June 2016.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/understanding-latency-variation-in-DRAM-chips_kevinchang_sigmetrics16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/understanding-latency-variation-in-DRAM-chips_kevinchang_sigmetrics16-talk.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/DRAM-Latency-Variation-Study">Source Code</a>]
</li>

<p><li>
     Donghyuk Lee, Samira Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-paper.pdf">"Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2017/"> ACM International Conference on Measurement and Modeling of Computer Systems</a> 
     (<b>SIGMETRICS</b>)</i>, Urbana-Champaign, IL, USA, June 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-abstract.pdf">Abstract</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-pomacs-onecolumn.pdf">POMACS Journal Version (same content, different format)</a>]
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/DIVA-low-latency-DRAM_sigmetrics17-talk.pdf">(pdf)</a>]
     <!--br>[<a href="https://github.com/CMU-SAFARI/DRAM-Latency-Variation-Study">Source Code</a>]-->
</li>

</ul>

<h4>Exploiting the Latency-Voltage-Reliability Tradeoffs for Energy and Security</h4>

<ul>

<p><li>
     Kevin Chang, A. Giray Yaglikci, Saugata Ghose, Aditya Agrawal, Niladrish Chatterjee, Abhijith Kashyap, Donghyuk Lee, Mike O'Connor, Hasan Hassan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-paper.pdf">"Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2017/"> ACM International Conference on Measurement and Modeling of Computer Systems</a> (<b>SIGMETRICS</b>)</i>, Urbana-Champaign, IL, USA, June 2017.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-abstract.pdf">Abstract</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-pomacs-onecolumn.pdf">POMACS Journal Version (same content, different format)</a>]
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-talk.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/DRAM-Voltage-Study">Full Data Sets and Circuit Model</a>]
</li>

<p><li>
     Jeremie S. Kim, Minesh Patel, Hasan Hassan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18.pdf">"The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern DRAM Devices"</a></b> <br>
     <i>Proceedings of the <a href="https://hpca2018.ece.ucsb.edu/">24th International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Vienna, Austria, February 2018.      
     <br>[<a href="https://www.youtube.com/watch?v=Xw0laEEDmsM&feature=youtu.be">Lightning Talk Video</a>]
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18_talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18_talk.pdf">(pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18_lightning-talk.pptx">Lightning Session Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18_lightning-talk.pdf">(pdf)</a>] 
     <!--br>[<a href="https://github.com/CMU-SAFARI/SoftMC">Source Code</a>]-->
</li>

</ul>

<h4>Reducing Refresh Latency</h4>

<ul>

<p><li>
     Anup Das, Hasan Hassan, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/VRL-DRAM_reduced-refresh-latency_dac18.pdf">"VRL-DRAM: Improving DRAM Performance via Variable Refresh Latency"</a></b><br>
     <i>Proceedings of the <a href="https://dac.com/">55th Design Automation Conference</a> (<b>DAC</b>)</i>, San Francisco, CA, USA, June 2018.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/VRL-DRAM_reduced-refresh-latency_dac18-talk.pdf">Slides (pdf)</a>] [<a href="https://people.inf.ethz.ch/omutlu/pub/VRL-DRAM_reduced-refresh-latency_dac18-poster.pdf">Poster (pdf)</a>]
     </li>

</ul>

<h4>Low-Latency Memory Architectures</h4>

<ul>

<p><li>
     Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/tldram_hpca13.pdf">"Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture"</a></b> <br>
     <i>Proceedings of the <a href="http://www.cs.utah.edu/~lizhang/HPCA19/">19th International Symposium on High-Performance Computer 
     Architecture</a> (<b>HPCA</b>)</i>, Shenzhen, China, February 2013.      <a href="https://people.inf.ethz.ch/omutlu/pub/lee_hpca13_talk.pptx">Slides (pptx)</a> 
</li>

<p><li>
     Kevin K. Chang, Prashant J. Nair, Saugata Ghose, Donghyuk Lee, Moinuddin K. Qureshi, and  <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/lisa-dram_hpca16.pdf">"Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM"</a></b> <br>
     <i>Proceedings of the <a href="http://hpca22.site.ac.upc.edu/">22nd International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Barcelona, Spain, March 2016.  
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/lisa-dram_kevinchang_hpca16-talk.pptx">Slides (pptx)</a> <a href="pub/lisa-dram_kevinchang_hpca16-talk.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/RamulatorSharp">Source Code</a>]
</li>

<p><li>
     Hasan Hassan, Gennady Pekhimenko, Nandita Vijaykumar, Vivek Seshadri, Donghyuk Lee, Oguz Ergin, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/chargecache_low-latency-dram_hpca16.pdf">"ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality"</a></b> <br>
     <i>Proceedings of the <a href="http://hpca22.site.ac.upc.edu/">22nd International Symposium on High-Performance Computer Architecture</a> (<b>HPCA</b>)</i>, Barcelona, Spain, March 2016.  
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/chargecache_low-latency-dram_hhassan_hpca16-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/chargecache_low-latency-dram_hhassan_hpca16-talk.pdf">(pdf)</a>]
     <br>[<a href="https://github.com/CMU-SAFARI/RamulatorSharp">Source Code</a>]
</li>

</ul>

<h4>Memory Power Consumption and Modeling</h4>

<ul>

<p><li>
     Saugata Ghose, A. Giray Yaglikci, Raghav Gupta, Donghyuk Lee, Kais Kudrolli, William X. Liu, Hasan Hassan, Kevin K. Chang, Niladrish Chatterjee, Aditya Agrawal, Mike O'Connor, and <u>Onur Mutlu</u>,<br>
     <b><a href="https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18_pomacs18.pdf">"What Your DRAM Power Models Are Not Telling You: Lessons from a Detailed Experimental Study"</a></b> <br>
     <i>Proceedings of the <a href="http://www.sigmetrics.org/sigmetrics2018/"> ACM International Conference on Measurement and Modeling of Computer Systems</a> (<b>SIGMETRICS</b>)</i>, Irvine, CA, USA, June 2018.
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18-abstract.pdf">Abstract</a>] 
     <!--[<a href="https://people.inf.ethz.ch/omutlu/pub/Voltron-reduced-voltage-DRAM-sigmetrics17-pomacs-onecolumn.pdf">POMACS Journal Version (same content, different format)</a>]-->
     <br>[<a href="https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18-talk.pptx">Slides (pptx)</a> <a href="https://people.inf.ethz.ch/omutlu/pub/VAMPIRE-DRAM-power-characterization-and-modeling_sigmetrics18-talk.pdf">(pdf)</a>]
     <!--<br>[<a href="https://github.com/CMU-SAFARI/DRAM-Voltage-Study">Full Data Sets and Circuit Model</a>]-->
</li>

</ul>

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