Minesh Patel awarded an ETH Doctoral Medal

We’d like to congratulate Minesh Patel on receiving an ETH Doctoral Medal for his outstanding Doctoral thesis.  Minesh’s dissertation, “Enabling Effective Error Mitigation in Modern Memory Chips that Use On-Die Error-Correcting Codes”, was nominated by the Department of Information Technology and Electrical Engineering (D-ITET), and will be presented at the Doctoral Awards Ceremony in January 2023.  This award is given to outstanding Master’s and Doctoral theses each year and recipients are honoured with a Silver Medal of ETH Zurich and a financial sum.

Minesh’s dissertation targets memory systems reliability — specifically, addressing DRAM technology scaling challenges, including DRAM refresh overheads and growing single-bit error rates. The dissertation contributes new techniques for understanding and identifying how errors manifest in modern DRAM chips, thereby enabling informed decision-making during system design.

Thesis Honors: 

For his thesis work, he also received the 2022 William C. Carter PhD Dissertation Award in Dependability, presented at DSN’22 in Baltimore in June.  The award was given in recognition of his significant contributions to the field of dependable and secure computing throughout his PhD dissertation.  He was recognized for his ground-breaking work in the handling of state-of-the-art error correction techniques opaquely implemented inside the newest DRAM chips.  Minesh’s PhD work addressed this challenging problem through experimental analyses of more than 300 DRAM chips, producing new statistical error models and tools, and building new system-level techniques to improve the chip’s error tolerance. Two of his PhD publications won Best Paper Awards (MICRO’20 and DSN’19), and his work has already had significant influence both in academia and industry, including on major DRAM manufacturers.

Moving Forward: 

Minesh is actively seeking a faculty position in which he can continue to advance the scientific state-of-the-art, and have influence in both academia and industry.  His work broadly focuses on computer and systems architecture topics, including (1) architecture, compiler, and runtime support for workloads on cutting-edge systems; (2) system design, analysis, modeling, and evaluation; and (3) building dependable, safe, and secure systems.  He enjoys the challenge of exploring, developing, and/or demonstrating candidate solutions to loosely-defined problems.

Beyond his PhD work, Minesh has research experience in a broad range of topics related to the memory system, including rethinking hardware and/or software to enable new functionality (e.g., virtual memory abstractionsin-memory computationsecurity primitives) and improve system-level metrics such as performanceenergy-efficiency, and security.

See his personal website for more details:  https://www.mineshp.com/


Minesh Patel, April 2022 (defended 01 October 2021)
Thesis title: “Enabling Effective Error Mitigation in Modern Memory Chips that Use On-Die Error-Correcting Codes”, [Slides (pptx) (pdf)] [Thesis arXiv (pdf)] [SAFARI Live Seminar Video]

Awards & Recognition: 

  • 2022 William C. Carter PhD Dissertation Award in Dependability
    Acceptance Speech
    , William C. Carter PhD Dissertation Award in Dependabilit
    y at DSN 2022 (Baltimore, MD), 28 June 2022. [Acceptance Speech Video] [Slides (pptx)(pdf)] [SAFARI News]
  • ISCA Hall of Fame
  • Best Paper Award for Patel et al., MICRO’20
    This work introduces BEER, a new memory testing technique capable of systematically determining the details of the error-correcting code used within a DRAM chip (i.e., on-die ECC). We demonstrate BEER’s correctness and practicality using a combination of real-chip and simulation-based experiments and release an open-source tool, BEER, to enable applying BEER to other DRAM chips.
  • Best Paper Award for Patel et al., DSN’19
    This work introduces EIN, a statistical inference methodology that uses MAP estimation to infer hidden details of both (1) the error-correcting code used within a memory chip; and (2) raw bit error characteristics. We demonstrate EIN in practice by applying it to real LPDDR4 DRAM chips and release an open-source tool, EINSim, to enable applying EIN to other DRAM chips.
Posted in Awards, Code, Interview, Papers, PhD Defense, Projects.