TRRespass wins the Pwnie Award for Most Innovative Research

TRRespass won the Pwnie Award for “Most Innovative Research” at the annual BlackHat Europe conference this week.  Pwnies are the most prestigious industrial awards in the security community.   Congratulations to the authors: Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi on this prestigious prize!

We recently interviewed Hasan Hassan about his contribution to TRRespass.  Here’s what he had to say:

You were a co-author on TRRespass, which recently won a Best Paper Award at IEEE S&P. What is the significance of this paper?

Shortly after the discovery of the RowHammer vulnerability of DRAM, DRAM vendors announced RowHammer-free DRAM devices that implement in-DRAM solutions to protect against RowHammer. However, in TRRespass, we find that such solutions, commonly referred to as Target Row Refresh (TRR), do not effectively protect against RowHammer attacks when many rows are hammered at the same time. We show that the RowHammer vulnerability is not only still intact on the current DDR4 devices, but it has also become worse due to technology node scaling.

How was your experience in collaborating with the Systems and Network Security Group at VU Amsterdam on this work?

I am glad that our combined effort with the Systems and Network Security Group at VU Amsterdam won us the Best Paper Award at IEEE S&P. It has been a great experience for me to collaborate with experts in hardware security. I hope there will be more such collaborations that result in impactful research.

Which tools did you use in this work?

I think SoftMC, our FPGA-based DRAM testing infrastructure, was one of the key enablers of this research. We used SoftMC to interface with DDR4 DRAM chips in a much more flexible way than anyone can do using commodity desktop and mobile systems. Specifically, we used SoftMC to communicate with DRAM chips using low-level DDR4 commands as opposed to using load/store instructions provided by typical instruction set architectures. In a way, SoftMC lets us be the memory controller and provides the flexibility of issuing any DDR4 command at any time, which is not possible with commodity systems.

An earlier version of SoftMC that supports DDR3 devices is open-source and can be accessed here. In 2017, we published a paper that describes the design of SoftMC in detail.

I am also involved in maintaining Ramulator, a cycle-accurate DRAM simulator that we describe in this paper, and Scarab, which is a cycle-accurate simulator for state-of-the-art multicore CPUs.


Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi, “TRRespass: Exploiting the Many Sides of Target Row Refresh”Proceedings of the 41st IEEE Symposium on Security and Privacy (S&P), San Francisco, CA, USA, May 2020.
Slides (pptx) (pdf)
Lecture Slides (pptx) (pdf)
Talk Video (17 minutes)
Lecture Video (59 minutes)
Source Code
Web Article
Project Overview
Best paper award.
Pwnie Award 2020 for Most Innovative Research. Pwnie Awards 2020

Paper: SneakySnake🐍: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

Our recent paper is accepted in Bioinformatics!

Mohammed Alser, Taha Shahroodi, Juan-Gomez Luna, Can Alkan, and Onur Mutlu,
“SneakySnake: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs”
Bioinformatics, to appear in 2020.

Source Code:  SneakySnake🐍: A Fast and Accurate Universal Genome Pre-Alignment Filter for CPUs, GPUs, and FPGAs

Radio Interview: Onur Mutlu discusses the review process

Listen to Onur Mutlu’s interview as he discusses the review process in the “ORF Dimensionen” broadcast on “Peer Review and Open Science”

How well does peer review work?
Interviewer: Mariann Unterluggauer
11 November 2020

The idea of using an assessment process to control the quality and efficiency of scientific work emerged in the middle of the 20th century. Since then, publishers have been using this “peer review” as a basis for making decisions about what should appear in their specialist journals. And anyone who wants to be awarded funding for their research projects must first go through and pass such an assessment process. However, this does not always work properly, as misjudgments and sloppiness have shown in the past. In addition, a positive “peer review” does not automatically mean that there is good or relevant science in a publication. – So what’s the point of peer review? Does the procedure have to be evaluated itself? Above all, the discussion about open science has stimulated the discussion about the review process of science.

Some useful related videos:

  • https://youtu.be/HvswnsfG3oQ?t=1800 (Onur Mutlu, Computer Architecture – Lecture 5c: Secure and Reliable Memory (ETH Zürich, Fall 2020): discussing the review process of RowHammer)
  • https://youtu.be/FYwOyapck3M?t=5421 (Onur Mutlu, Seminar in Computer Architecture – Lecture 2: RowClone – In-Memory Data Copy (ETH Zürich, Fall 2020): discussing the review process of RowClone)
  • https://youtu.be/yEYEzFwAY9g?t=4445 (Onur, Mutlu, Seminar in Computer Architecture – Lecture 3: Memory Channel Partitioning (ETH Zürich, Fall 2020): discussing the review process of Memory Channel Partitioning)

We are at MICRO 2020 this week! Join Lois Orosa for his talk on FIGARO, Monday, October 19 6:30PM CEST

Our new paper: FIGARO: Improving System Performance via Fine-Grained In-DRAM Data Relocation and Caching will be presented by Lois Orosa at MICRO 2020 on Monday, October 19 at 6:30 PM CEST.  Join us at MICRO 2020 online!

Authors: Yaohua Wang, Lois Orosa, Xiangjun Peng, Yang Guo, Saugata Ghose, Minesh Patel, Jeremie S. Kim, Juan Gómez Luna, Mohammad Sadrosadati, Nika Mansouri Ghiasi, and Onur Mutlu

Proceedings of the 53rd International Symposium on Microarchitecture (MICRO), Virtual, October 2020.
[Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (16 minutes)]
[Lightning Talk Video (1.5 minutes)]

Best Paper Award MICRO 2020: Congratulations Minesh Patel and co-authors!

Our new paper: Bit-Exact ECC Recovery (BEER): Determining DRAM On-Die ECC Functions by Exploiting DRAM Data Retention Characteristics  will be presented by Minesh Patel at MICRO 2020 on Monday, October 19 at 6:00 PM CEST.  Join us at MICRO 2020 online!

Update: This paper won the Best Paper Award!  Congratulations to Minesh Patel and co-authors: Jeremie S. Kim, Taha Shahroodi, Hasan Hassan, and Onur Mutlu,

We asked Minesh a couple questions about his paper, here’s what he had to say:

You recently won the Best Paper Award at MICRO.  Can you tell us more about the
significance of this paper?
This paper addresses the larger problem that hidden proprietary features
implemented by DRAM manufacturers impede end-users from bringing out the best of
DRAM technology. We believe BEER takes an important step towards bridging the
gap between industry and end-users, starting by focusing on a key example of
such features: on-die ECC. Our work discusses how and why on-die ECC limits
third-party DRAM consumers and then introduces techniques that the consumers can
use to overcome these limitations.

What were the biggest challenges for you during the writing and review process?I would say that the biggest challenge we faced when writing this paper was to
clearly articulate the problem of on-die ECC limiting third-party users. This
includes both (i) describing how and why this limitation arises and (ii)
providing concrete examples that the reader can relate to. We spent considerable
effort in crafting these arguments such that both we and the reader have a clear
understanding of the problem we tackle, our goal in this work, and the final
value of our contributions.

Proceedings of the 53rd International Symposium on Microarchitecture (MICRO), Virtual, October 2020.
[Slides (pptx) (pdf)]
[Short Talk Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (15 minutes)]
[Short Talk Video (5.5 minutes)]
[Lightning Talk Video (1.5 minutes)]
[BEER Source Code]

Paper MICRO 2020: Join Damla Senol Cali for her talk on Wednesday, October 21, 7PM CEST

Damla Senol Cali will present: GenASM: A High-Performance, Low-Power Approximate String Matching Acceleration Framework for Genome Sequence Analysis, Wednesday, October 21 at 7:00 PM CEST.

Authors: Damla Senol Cali, Gurpreet S. Kalsi, Zulal Bingol, Can Firtina, Lavanya Subramanian, Jeremie S. Kim, Rachata Ausavarungnirun, Mohammed Alser, Juan Gomez-Luna, Amirali Boroumand, Anant Nori, Allison Scibisz, Sreenivas Subramoney, Can Alkan, Saugata Ghose, and Onur Mutlu,

Proceedings of the 53rd International Symposium on Microarchitecture (MICRO), Virtual, October 2020.
[ARM Research Summit Talk Video (21 minutes)]
[ARM Research Summit Short Talk Video (15 minutes)]
[ARM Research Summit Short Talk Video and Q&A (31 minutes)]
[ARM Research Summit Talk Slides (pptx) (pdf)]
[ARM Research Summit Short Talk Slides (pptx) (pdf)]
[Lighting Talk Video (1.5 minutes)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (18 minutes)]
[Slides (pptx) (pdf)]

Paper MICRO 2020: Join Jawad Haj-Yahya for his talk Wednesday, October 21, 7:30PM CEST

Join Jawad Haj-Yahya for his MICRO 2020 talk where he will present our paper: FlexWatts: A Power- and Workload-Aware Hybrid Power Delivery Network for Energy-Efficient Microprocessors, Wednesday October 21 at 7:30 PM CEST.

Authors: Jawad Haj-Yahya, Mohammed Alser, Jeremie S. Kim, Lois Orosa, Efraim Rotem, Avi Mendelson, Anupam Chattopadhyay, and Onur Mutlu,

Proceedings of the 53rd International Symposium on Microarchitecture (MICRO), Virtual, October 2020.
[Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (15 minutes)]
[Lightning Talk Video (1.5 minutes)]

Talk: Intelligent Architectures for Intelligent Machines Oct 7

Join Onur for his online talk in the HKUST Engineering x HKSTP Distinguished Speaker Series on Oct 7 at 11:00 CEST (Zurich time).

You can register here: https://calendar.ust.hk/events/hkust-engineering-x-hkstp-distinguished-speaker-series-webinar-intelligent-architectures

Computing is bottlenecked by data. Large amounts of application data overwhelm storage capability, communication capability, and computation capability of the modern machines we design today. As a result, many key applications’ performance, efficiency and scalability are bottlenecked by data movement.

Jointly hosted by SENG, HKUST AI Chip Center for Emerging Smart Systems and Hong Kong Science and Technology Parks Corporation, this webinar features a renowned computer architecture expert, Prof. Onur Mutlu from ETH Zurich. We will discuss the major shortcomings of modern architectures, the recent research that could enable computation close to data, as well as the guiding principles for future computing architecture and system designs. (Please click here for more information.)

Moderated by Prof. Tim Cheng, Dean of Engineering, register to get more insights on how intelligent architecture could be designed to handle data well.

Award: Jisung Park was awarded a Postdoctoral Research Fellowship

Jisung Park was awarded a Postdoctoral Research Fellowship from the National Research Foundation of Korea for his project on “Storage System Design for Machine Learning Applications”.

Congratulations Jisung — We look forward to having you in the group for another year!

The NRF Postdoctoral Research Fellowship supports promising Korean postdoctoral researchers in all fields of science and engineering for one year.