Paper: Accelerating Genome Analysis: A Primer on an Ongoing Journey

Posted on by

In our new paper, we describe the ongoing journey in significantly improving the performance of read mapping: Accelerating Genome Analysis: A Primer on an Ongoing Journey

Mohammed Alser, Zülal Bingöl, Damla Senol Cali, Jeremie Kim, Saugata Ghose, Can Alkan, Onur Mutlu

Paper, arXiv: https://people.inf.ethz.ch/omutlu/pub/AcceleratingGenomeAnalysis_ieeemicro20.pdf
Paper, IEEE Micro: https://www.computer.org/csdl/magazine/mi/2020/05/09154510/1lZzYVaH7lC

Invited Talks

Mohammed Alser:
A Roadmap for Fast and Efficient Genome Analysis, Univ. of Tokyo, Shirokanedai:
https://www.youtube.com/watch?v=DTfNzcYIgOI&feature=youtu.be

Mohammed Alser:
Accelerating Genome Analysis Using New Algorithms and Hardware Designs, Univ. of Tokyo: https://www.youtube.com/watch…

Onur Mutlu:
AACBB 2019 Keynote Talk: https://www.youtube.com/watch?v=hPnSmfwu2-A

Paper: NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling

Posted on by

Gagandeep Singh presented his work on “NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling” yesterday at the International Conference on Field-Programmable Logic and Applications (FPL) 2020.

Co-authors: Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez Luna, Onur Mutlu, Sander Stuijk, Henk Corporaal

This work has also been nominated for the Stamatis Vassiliadis Memorial Award at #FPL2020!

Gagandeep Singh, Dionysios Diamantopoulos, Christoph Hagleitner, Juan Gómez-Luna, Sander Stuijk, Onur Mutlu, and Henk Corporaal,
“NERO: A Near High-Bandwidth Memory Stencil Accelerator for Weather Prediction Modeling”
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications (FPL), Gothenburg, Sweden, September 2020.
[Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (23 minutes)]
Nominated for the Stamatis Vassiliadis Memorial Award.

Keynote talk: How can we make computing architectures intelligent? VLSI-TSA/VLSI-DAT 2020

Posted on by

Onur Mutlu gave a keynote talk and paper on “Intelligent Architectures for Intelligent Machines” at VLSI-TSA and VLSI-DAT 2020:

Onur Mutlu,
“Intelligent Architectures for Intelligent Machines”
Plenary Keynote Talk at the 2020 International Symposia on VLSI (VLSI), Virtual, 11 August 2020.
[Slides (pptx) (pdf)]
[Talk Video (55 minutes)]
[Keynote Paper]

Keynote talk: Designing more principled system architectures: DAC2020

Posted on by

How can we design more principled system architectures to solve the data handling problem? Onur Mutlu talked this week during the Design Automation Conference Tutorial on “Toward New Era of Compute-in-Memory: From Memory Devices to Applications“:

Onur Mutlu,
“Computation in Memory: An Architectural Perspective”
57th Design Automation Conference Tutorial on New Era of Compute-In-Memory (DAC), Virtual, 20 July 2020.
[Slides (pptx) (pdf)]

 

Talk: How to Build an Impactful Research Group: DAC Early Career Workshop

Posted on by

Do you want to learn “How to Build an Impactful Research Group”? Onur Mutlu joined Tulika Mitra, Jürgen Teich, and Helen Li for the panel discussion at the Design Automation Conference Early Career Workshop and shared his insights:

Onur Mutlu,
“How to Build an Impactful Research Group”
57th Design Automation Conference Early Career Workshop (DAC), Virtual, 19 July 2020.
[Slides (pptx) (pdf)]

Papers: We are at ISCA 2020 this week (virtually)!

Posted on by

We are attending ISCA 2020 this week, 29 May – 3 June, online: https://iscaconf.org/isca2020/.

Congratulations to Nastaran Hajinazar on winning the photo contest!

We are excited to be presenting several papers this year — join us for our talks, or watch the recordings any time:

Jeremie S. Kim, Minesh Patel, A. Giray Yaglikci, Hasan Hassan, Roknoddin Azizi, Lois Orosa, and Onur Mutlu,
“Revisiting RowHammer: An Experimental Analysis of Modern Devices and Mitigation Techniques”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (20 minutes)]

Haocong Luo, Taha Shahroodi, Hasan Hassan, Minesh Patel, A. Giray Yaglikci, Lois Orosa, Jisung Park, and Onur Mutlu,
“CLR-DRAM: A Low-Cost DRAM Architecture Enabling Dynamic Capacity-Latency Trade-Off”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (20 minutes)]

Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo Francisco de Oliveira Jr., Jonathan Appavoo, Vivek Seshadri, and Onur Mutlu,
“The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]
[Talk Video (26 minutes)]

Jawad Haj-Yahya, Mohammed Alser, Jeremie Kim, A. Giray Yaglikci, Nandita Vijaykumar, Efraim Rotem, and Onur Mutlu,
“SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors”
Proceedings of the 47th International Symposium on Computer Architecture (ISCA), Valencia, Spain, June 2020.
[Slides (pptx) (pdf)]

Award: TRRespass wins the Best Paper Award at IEEE S&P!

Posted on by

Our recent paper “TRRespass: Exploiting the Many Sides of Target Row Refresh”, in collaboration with the Systems and Network Security Group at VU Amsterdam has been awarded the Best Paper Award at the 41st IEEE Symposium on Security and Privacy!

Congratulations to the authors: Pietro Frigo, Emanuele Vannacci, Hasan Hassan, Victor van der Veen, Onur Mutlu, Cristiano Giuffrida, Herbert Bos, and Kaveh Razavi

Rowhammer, the DRAM vulnerability that was supposedly fixed in DDR4 is not fixed in DDR4. The TRRespass attack shows that DIMMs from all 3 major vendors (good for 95% of the market) are still vulnerable.

Read the news story: NakedSecurity
Paper: “TRRespass: Exploiting the Many Sides of Target Row Refresh”
Talk Video
Source Code
Project Overview