DRAM is predominantly used to build the main memory systems of modern computing devices. Simulation-based experimental studies are key for understanding the complex interactions between DRAM and modern applications.
Ramulator is an extensible DRAM simulator providing cycle-accurate performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM) and academic proposals. Ramulator has a modular design that enables easy integration of additional DRAM standards and mechanisms. Ramulator is written in C++11 and can be easily integrated to full-system simulators such as gem5.
In this P&S, you will design new DRAM and memory controller mechanisms for improving overall system performance, energy consumption, and reliability. You will extend Ramulator with these new designs and evaluate their performance, energy consumption, and reliability using modern applications. This will be the right P&S for you if you would like to learn about the state-of-the-art memory controller and DRAM designs and their interaction with modern applications. This P&S will also enable you to hands-on simulate and understand the memory system behavior of modern workloads such as machine learning, graph analytics, genome analysis.
Prerequisites of the course:
The course is conducted in English.
Mailing List: firstname.lastname@example.org (sent to all mentors)
|Lead Supervisor||Hasan Hassanemail@example.com||ETZ H 61.2|
|Supervisor||Geraldo de Oliveirafirstname.lastname@example.org||ETZ H 61.2|
|Supervisor||Lois Orosaemail@example.com||ETZ H 61.2|
|Supervisor||Giray Yaglikcifirstname.lastname@example.org||ETZ H 61.2|
|Supervisor||Minesh Patelemail@example.com||ETZ H 61.2|
|Supervisor||Haocong Luofirstname.lastname@example.org||ETZ H 61.2|
|W1|| 14.10 |
| M1: Logistics & Intro to Simulating Memory Systems Using Ramulator |
|W2|| 22.10 |
| M2: Using Ramulator to Evaluate New DRAM and Memory Controller Mechanisms |
| M2a. CROW |
| M2b. BlockHammer |
| M2c. CLR-DRAM |