SAFARI Project & Seminars Courses (Fall 2022)

Data movement between the memory units and the compute units of current computing systems is a major performance and energy bottleneck. From large-scale servers to mobile devices, data movement costs dominate computation costs in terms of both performance and energy consumption. For example, data movement between the main memory and the processing cores accounts for 62% of the total system energy in consumer applications. As a result, the data movement bottleneck is a huge burden that greatly limits the energy efficiency and performance of modern computing systems. This phenomenon is an undesired effect of the dichotomy between memory and the processor, which leads to the data movement bottleneck.

Many modern and important workloads such as machine learning, computational biology, graph processing, databases, video analytics, and real-time data analytics suffer greatly from the data movement bottleneck. These workloads are exemplified by irregular memory accesses, relatively low data reuse, low cache line utilization, low arithmetic intensity (i.e., ratio of operations per accessed byte), and large datasets that greatly exceed the main memory size. The computation in these workloads cannot usually compensate for the data movement costs. In order to alleviate this data movement bottleneck, we need a paradigm shift from the traditional processor-centric design, where all computation takes place in the compute units, to a more data-centric design where processing elements are placed closer to or inside where the data resides. This paradigm of computing is known as Processing-in-Memory (PIM).

This is your perfect P&S if you want to become familiar with the main PIM technologies, which represent “the next big thing” in Computer Architecture. You will work hands-on with the first real-world PIM architecture, will explore different PIM architecture designs for important workloads, and will develop tools to enable research of future PIM systems. Projects in this course span software and hardware as well as the software/hardware interface. You can potentially work on developing and optimizing new workloads for the first real-world PIM hardware or explore new PIM designs in simulators, or do something else that can forward our understanding of the PIM paradigm.

Prerequisites of the course:

• Digital Design and Computer Architecture (or equivalent course).
• Familiarity with C/C++ programming.
• Interest in future computer architectures and computing paradigms.
• Interest in discovering why things do or do not work and solving problems
• Interest in making systems efficient and usable

The course is conducted in English.

The course has two main parts:
1. Weekly lectures on processing-in-memory.
2. Hands-on project: Each student develops his/her own project.

Course description page Moodle

Fall 2022 Lecture Playlist

Spring 2022 Lecture Playlist

Fall 2021 Lecture Playlist

• Processing Data Where It Makes Sense: Enabling In-Memory Computation (summary paper about recent research in PIM):
  • PDF
• Processing Data Where It Makes Sense in Modern Computing Systems: Enabling In-Memory Computation (keynote talk ICCD 2019):
  • PDF PPT Video

• Processing-in-memory: A workload-driven perspective (summary paper about recent research in PIM):
  • PDF
• Computation in Memory (Professor Onur Mutlu, lecture, Fall 2019):
  • PDF PPT Video
• Computation in Memory II (Professor Onur Mutlu, lecture, Fall 2019):
  • PDF PPT Video
• Computation in Memory III (Professor Onur Mutlu, lecture, Fall 2019):
  • PDF PPT Video

• Ramulator-PIM: A version of Ramulator simulator for PIM
• UPMEM SDK documentation: The first real-world PIM architecture
• An example recent study of 3D-stacked PIM for consumer workloads
• An example recent study of lightweight PIM functionality on 3D-stacked memory
• An example recent study of a PIM accelerator for graph processing
• An example recent study of a Processing-using-Memory system:
  • Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology
  • In-DRAM Bulk Bitwise Execution Engine

• HW0 handout