DRAM is predominantly used to build the main memory systems of modern computing devices. Emerging memory technologies (RRAM, PCM, STT-MRAM, FeRAM) provide an exciting opportunity to replace or complement DRAM. Simulation-based experimental studies are key for understanding the complex interactions between DRAM, emerging memory technologies, and modern applications. Ramulator is an extensible main memory simulator providing cycle-accurate performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM), emerging memory technologies, and academic proposals. Ramulator has a modular design that enables easy integration of additional standards, technologies and mechanisms. Ramulator is written in C++11 and can be easily integrated to full-system simulators such as gem5.
In this P&S, you will design new memory and memory controller mechanisms for improving overall system performance, energy consumption, reliability, security, scalability and cost. You will extend Ramulator with these new designs and evaluate their performance, energy consumption, and reliability using modern applications.
This will be the right P&S for you if you would like to learn about the state-of-the-art and future memory and memory controller designs and their interaction with modern applications. This P&S will also enable you to hands-on simulate and understand the memory system behavior of modern workloads such as machine learning, graph analytics, genome analysis.
Prerequisites of the course:
The course is conducted in English.
Mailing List: firstname.lastname@example.org (sent to all mentors)
|Lead Supervisor||Haocong Luoemail@example.com||ETZ H 61.2|
|Supervisor||Giray Yaglikcifirstname.lastname@example.org||ETZ H 61.2|
|Supervisor||Geraldo de Oliveiraemail@example.com||ETZ H 61.2|
|Supervisor||Ataberk Olgunfirstname.lastname@example.org||ETZ H 61.2|