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FPGA-based Exploration of DRAM and RowHammer 227-0085-35L P&S

Course Description

DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.

DRAM Bender (a.k.a. SoftMCv2) is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. DRAM Bender provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level DRAM Bender instructions in the FPGA. DRAM Bender hardware developers write low-level hardware description language code to enable new and faster studies.

In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using DRAM Bender while developing DRAM test programs for new DRAM characterization studies related to performance, reliability, and security. You may also improve the DRAM Bender infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.

This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.

Prerequisites of the course:

  • Digital Design and Computer Architecture (or equivalent course)
  • Familiarity with FPGA programming
  • Interest in low-level system exploration and memory
  • Interest in discovering why things do or do not work and solving problems

The course is conducted in English.

Course description page Moodle


Mailing List: (sent to all mentors)

Name E-mail Office
Lead Supervisor Ataberk Olgun ETZ H 61.2
Supervisor Giray Yaglikci ETZ H 61.2
Supervisor Haocong Luo ETZ H 61.2
Supervisor Yahya Tugrul ETZ H 61.2
Supervisor Banu Cavlak ETZ H 61.1
Supervisor Ismail Yuksel

Lecture Video Playlist on YouTube (Previous Semester: Spring 2022)

Fall 2022 Meetings/Schedule (Tentative)

Week Date Livestream Meeting Learning Materials Assignments
W0 30.09
P&S SoftMC Tutorial SoftMC Tutorial Slides
W1 04.10
P&S DRAM Bender: Introduction and Logistics Meeting Slides
W2 11.10
P&S DRAM Bender: DRAM Bender Tutorial and Project Descriptions Meeting Slides
W3 18.10
P&S DRAM Bender: A Deeper Look into RowHammer's Sensitivities: Analysis, Attacks & Defenses No Slides
W4 25.10
P&S DRAM Bender: Uncovering TRR: New Methodology, Custom RowHammer Patterns & Implications Meeting Slides
W5 02.11
P&S DRAM Bender: HiRA – Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips Meeting Slides
W6 09.11
No Video P&S DRAM Bender: First Group Meeting Meeting Slides
W7 15.11
P&S DRAM Bender: QUAC-TRNG – High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips

Learning Materials

Meeting 1: Required Materials

Meeting 1: Recommended Materials

More Learning Materials


HW0: Student Information (Due: 07.10)

softmc.txt · Last modified: 2022/11/13 14:39 by aolgun