Genome analysis is a cornerstone for groundbreaking scientific and medical advancements, including personalized healthcare. However, the field faces significant computational challenges, such as algorithmic bottlenecks and the handling of large datasets. This course aims to provide a comprehensive understanding of these computational facets, spanning across the computing stack from algorithms, software & tools, to microarchitecture & hardware accelerators.

The course will cover how advanced hardware solutions like FPGAs and GPUs can expedite genome analysis by reducing computational time and energy consumption. In parallel, it will delve into the use and development of heuristic algorithms & tools for accelerating genome analysis across various computational platforms. These algorithms, for example, can offer tradeoffs between computational intensity and accuracy. Students will engage in hands-on projects focused on optimizing existing methods or innovating new solutions for genome analysis. The curriculum’s dual emphasis on hardware solutions and versatile algorithmic strategies offers students a holistic view of the current challenges and potential resolutions within the realm of genome analysis.

Prerequisites of the course:

• No prior knowledge in bioinformatics or genome analysis is required.
• An interest in optimizing efficiency and solving complex problems is essential.
• Basic to good knowledge in C or C++ programming language is required.
• Previous coursework in Digital Design and Computer Architecture, or an equivalent course, is desirable.
• Experience in either FPGA implementation, GPU programming, or algorithm design is highly beneficial but not mandatory.

The course is conducted in English.

Course description page
Moodle

Mentors

Lecture Playlist (Fall 2023):

Complete Lecture Playlist (Spring 2023):

• An Overview paper on co-designing hardware and software for accelerating genome analysis: PDF
• A survey on the main steps in the genome analysis pipeline and their bottlenecks: PDF
• A survey on accelerating genome analysis: PDF
• A detailed survey on the state-of-the-art algorithms for sequencing data: PDF
• An example of how to accelerate genomic sequence matching by two orders of magnitude with the help of FPGAs or GPUs: PDF
• Example of using a different computing paradigms for accelerating read mapping and read alignment steps and improving its energy consumption: PDF1 PDF2
• Examples on using software/hardware co-design to accelerate genomic sequence matching: PDF1 PDF2 PDF3 PDF4
• An example on analyzing raw nanopore signals: PDF

You are welcome to attend this seminar on Wednesday.

Time & Date: Wednesday, October 4, 14:00 Zurich time

Where: HG E23 & Livestream on YouTube

Title: Reshaping DRAM Scaling by Enabling System-Memory Cooperation

Abstract: Today’s DRAM suffers from worsening technology scaling challenges that threaten the continued growth of all DRAM-based systems. Overcoming these challenges requires new solutions driven by both DRAM producers and consumers. Unfortunately, the way we design and use DRAM today is becoming a significant limiting factor in addressing scaling-related concerns. In this talk, I will discuss our ongoing work that studies how the division of responsibilities between DRAM producers and consumers constrains each party’s overall solution space. I will review four promising directions for overcoming DRAM scaling challenges through system-memory cooperation. I will then discuss how, in each case, the most important barrier to advancement is the consumer’s lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, I will recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, I will propose adopting this revision in a two-step plan, i) initially starting with immediate information release through crowdsourcing and publications and ii) culminating in targeted modifications to industry-wide DRAM standards.

Speaker Bio: Minesh Patel received his DSc from ETH Zürich and dual BS degrees from UT Austin in physics and electrical engineering. His doctoral thesis focuses on overcoming performance, reliability, and security challenges in the memory system. In particular, his dissertation identifies and addresses new challenges for system-level error detection and mitigation targeting memory chips with integrated error correcting codes (ECC). He also worked collaboratively on understanding and solving the RowHammer vulnerability, near-data processing, efficient virtual memory management, and new hardware security primitives. Minesh’s graduate work has been recognized with several honors, including DSN’19 and MICRO’20 Best Paper Awards, the William Carter Dissertation Award in Dependability, the ETH Doctoral Medal, and induction into the ISCA Hall of Fame.