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FPGA-based Exploration of DRAM and RowHammer 227-0085-35L P&S

Course Description

DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.

DRAM Bender (a.k.a. SoftMCv2) is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. DRAM Bender provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level DRAM Bender instructions in the FPGA. DRAM Bender hardware developers write low-level hardware description language code to enable new and faster studies.

In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using DRAM Bender while developing DRAM test programs for new DRAM characterization studies related to performance, reliability, and security. You may also improve the DRAM Bender infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.

This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.

Prerequisites of the course:

  • Digital Design and Computer Architecture (or equivalent course)
  • Familiarity with FPGA programming
  • Interest in low-level system exploration and memory
  • Interest in discovering why things do or do not work and solving problems
  • Basic proficiency in programming (we use C++/Python)

The course is conducted in English.

Course description page Moodle


Mailing List: (sent to all mentors)

Name E-mail Office
Lead Supervisor Ataberk Olgun OAT U13
Supervisor A. Giray Yaglikci ETZ H 61.2
Supervisor Haocong Luo ETZ H 61.2
Supervisor Yahya Tugrul
Supervisor Ismail Yuksel OAT U13

Lecture Video Playlist on YouTube (Previous Semester: Spring 2023)

Spring 2023 Meetings/Schedule

Week Date Livestream Meeting Learning Materials Assignments
Introduction & Logistics (Past Edition) Slides
DRAM Bender Tutorial (Past Edition)
W1 03.10.2023 P&S DRAM Bender:
Introduction & Logistics
HW 0
W2 11.10.2023 P&S DRAM Bender:
W3 18.10.2023 Weekly Update Meeting &
Research Paper Presentation:
Experimental Analysis of RowHammer in HBM2
W4 25.10.2023 Weekly Update Meeting &
Research Paper Presentation:
Uncovering in-DRAM TRR
W5 01.11.2023 Weekly Update Meeting &
Research Paper Presentation:
W6 08.11.2023 Weekly Update Meeting &
Research Paper Presentation:
RowHammer Under Reduced Voltage
W7 15.11.2023 Weekly Update Meeting

Learning Materials

Meeting 1: Required Materials

Meeting 1: Recommended Materials

More Learning Materials


HW0: Student Information (Due: 07.10)


October 02, 2023

SAFARI Live Seminar (Wednesday 04.10, 2pm): Reshaping DRAM Scaling by Enabling System-Memory Cooperation

Dear Computer Architecture Students,

You are welcome to attend this seminar on Wednesday.

Time & Date: Wednesday, October 4, 14:00 Zurich time

Where: HG E23 & Livestream on YouTube

Title: Reshaping DRAM Scaling by Enabling System-Memory Cooperation

Abstract: Today’s DRAM suffers from worsening technology scaling challenges that threaten the continued growth of all DRAM-based systems. Overcoming these challenges requires new solutions driven by both DRAM producers and consumers. Unfortunately, the way we design and use DRAM today is becoming a significant limiting factor in addressing scaling-related concerns. In this talk, I will discuss our ongoing work that studies how the division of responsibilities between DRAM producers and consumers constrains each party’s overall solution space. I will review four promising directions for overcoming DRAM scaling challenges through system-memory cooperation. I will then discuss how, in each case, the most important barrier to advancement is the consumer’s lack of insight into DRAM reliability. Based on an analysis of DRAM reliability testing, I will recommend revising the separation of concerns to incorporate limited information transparency between producers and consumers. Finally, I will propose adopting this revision in a two-step plan, i) initially starting with immediate information release through crowdsourcing and publications and ii) culminating in targeted modifications to industry-wide DRAM standards.

Speaker Bio: Minesh Patel received his DSc from ETH Zürich and dual BS degrees from UT Austin in physics and electrical engineering. His doctoral thesis focuses on overcoming performance, reliability, and security challenges in the memory system. In particular, his dissertation identifies and addresses new challenges for system-level error detection and mitigation targeting memory chips with integrated error correcting codes (ECC). He also worked collaboratively on understanding and solving the RowHammer vulnerability, near-data processing, efficient virtual memory management, and new hardware security primitives. Minesh’s graduate work has been recognized with several honors, including DSN’19 and MICRO’20 Best Paper Awards, the William Carter Dissertation Award in Dependability, the ETH Doctoral Medal, and induction into the ISCA Hall of Fame.

dram_bender.txt · Last modified: 2023/11/14 16:36 by aolgun