DRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.
SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies.
In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability, and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.
This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.
Prerequisites of the course:
The course is conducted in English.
|Lead Supervisor||Hasan Hassanfirstname.lastname@example.org||ETZ H 61.2|
|Supervisor||Jeremie Kimemail@example.com||ETZ H 61.1|
|Supervisor||Lois Orosafirstname.lastname@example.org||ETZ H 61.2|
|Supervisor||Minesh Patelemail@example.com||ETZ H 61.2|
|Supervisor||Giray Yaglikcifirstname.lastname@example.org||ETZ H 61.2|