SAFARI Live Seminar: Hasan Hassan, Sept 15 2022

Abstract:
As DRAM scales down to smaller technology nodes, it faces key challenges in both data integrity and latency, which strongly affect overall system reliability, security, and performance. To develop reliable, secure, and high-performance DRAM-based main memory for future systems, it is critical to rigorously characterize, analyze, and understand various aspects (e.g., reliability, retention, latency, RowHammer vulnerability) of existing DRAM chips and their architecture. Our goal is to 1) develop techniques and infrastructures to enable such rigorous characterization, analysis, and understanding, and 2) enable new mechanisms to improve DRAM performance, reliability, and security based on the developed understanding.

In this seminar, we present four contributions that we make towards achieving our goal. First, to easily study the reliability characteristics and the operation of real DRAM chips, we design and prototype SoftMC (Soft Memory Controller), a flexible and easy-to-use experimental DRAM testing infrastructure. SoftMC offers a wide range of use cases, such as characterizing the effects of variation within a DRAM chip and across DRAM chips, verifying the correctness of new DRAM mechanisms on actual hardware, and experimentally discovering the reliability, retention, and timing characteristics of an unknown or newly-designed DRAM chip (or finding the best specifications for a known DRAM chip). Second, we use SoftMC to study the security guarantees of RowHammer protection mechanisms, called Target Row Refresh (TRR), that DRAM vendors implement in their chips. We develop Uncovering TRR (U-TRR), a new experimental methodology to analyze in-DRAM TRR implementations. U-TRR allows us to (i) understand how logical DRAM rows are laid out physically in silicon; (ii) study undocumented on-die TRR mechanisms; and (iii) combine (i) and (ii) to evaluate the RowHammer security guarantees of modern DRAM chips. We show how U-TRR allows us to craft RowHammer access patterns that successfully circumvent the TRR mechanisms employed in 45 DRAM modules of the three major DRAM vendors. Third, to ease the process of implementing new and efficient DRAM maintenance operations (e.g., refresh, RowHammer protection, memory scrubbing), we propose Self-Managing DRAM (SMD). SMD is a new low-cost DRAM architecture that enables implementing new in-DRAM maintenance mechanisms with no further changes in the DRAM interface, memory controller, or other system components. Our evaluations show that SMD-based maintenance operations have significantly lower system performance and energy overheads compared to conventional DDR4 DRAM. Fourth, we propose Copy-Row DRAM (CROW), a flexible substrate that enables new mechanisms for improving DRAM performance, energy efficiency, and reliability. We use the CROW substrate to implement 1) a low-cost in-DRAM caching mechanism that lowers DRAM activation latency to frequently-accessed rows by 38% and 2) a mechanism that avoids the use of short-retention-time rows to mitigate the performance and energy overhead of DRAM refresh operations. 

Speaker Bio:
Hasan Hassan is a Ph.D. candidate at ETH Zurich working with Prof. Onur Mutlu. He received B.S. and M.S. degrees in Computer Engineering from TOBB University of Economics & Technology in 2014 and 2016. His research interests broadly span computer architecture topics with a particular focus on memory systems and their performance, efficiency, reliability, and security problems.

Relevant work:

Hasan Hassan, Ataberk Olgun, A. Giray Yaglikci, Haocong Luo, Onur Mutlu, “A Case for Self-Managing DRAM Chips: Improving Performance, Efficiency, Reliability, and Security via Autonomous in-DRAM Maintenance Operations”, Preprint on arXiv, July 2022.

Hasan Hassan, Yahya Can Tugrul, Jeremie S. Kim, Victor van der Veen, Kaveh Razavi, and Onur Mutlu, “Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHammer Patterns, and Implications”, Proceedings of the 54th International Symposium on Microarchitecture (MICRO), Virtual, October 2021.
[Slides (pptx) (pdf)]
[Short Talk Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Talk Video (25 minutes)]
[Lightning Talk Video (100 seconds)]
[arXiv version]

Hasan Hassan, Minesh Patel, Jeremie S. Kim, A. Giray Yaglikci, Nandita Vijaykumar, Nika Mansourighiasi, Saugata Ghose, and Onur Mutlu, “CROW: A Low-Cost Substrate for Improving DRAM Performance, Energy Efficiency, and Reliability”,  Proceedings of the 46th International Symposium on Computer Architecture (ISCA), Phoenix, AZ, USA, June 2019.
[Slides (pptx) (pdf)]
[Lightning Talk Slides (pptx) (pdf)]
[Poster (pptx) (pdf)]
[Lightning Talk Video (3 minutes)]
[Full Talk Video (16 minutes)]
[Full Talk Lecture (29 minutes)]
[Source Code for CROW (Ramulator and Circuit Modeling)]

Hasan Hassan, Nandita Vijaykumar, Samira Khan, Saugata Ghose, Kevin Chang, Gennady Pekhimenko, Donghyuk Lee, Oguz Ergin, and Onur Mutlu, “SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies”,  Proceedings of the 23rd International Symposium on High-Performance Computer Architecture (HPCA), Austin, TX, USA, February 2017.
[Slides (pptx) (pdf)] [Lightning Session Slides (pptx) (pdf)]
[Full Talk Lecture (39 minutes)]
[Source Code]