Join us for our upcoming SAFARI Live Seminar.
Date: Monday, August 21 2023, 15:00 Zurich time (CEST)
Where: Livestream on YouTube (Link) & ETZ J 91
Title: A Potpourri of Ideas and Results in DRAM, FPGA Infrastructures, and RISC-V Processors
In this talk, I will give an overview of some recent ideas and results in DRAM based random number generation, FPGA based DRAM testing and evaluation infrastructures, undervolting in FPGAs, and RISC-V processor design.
This presentation will cover innovative advancements in True Random Number Generators (TRNGs) and FPGA efficiency. Specifically, the talk describes QUAC-TRNG, a high-throughput TRNG that can be implemented in commodity DRAM chips, demonstrating substantial improvements in throughput and utilization compared to state-of-the-art DRAM-based TRNGs. It also introduces DR-STRaNGe, an end-to-end system design addressing the key challenges associated with DRAM-based TRNGs, achieving significant improvements in performance, fairness, and energy consumption. The talk will outline a new experimental infrastructure, DRAM Bender, and briefly discuss the Processing-in-DRAM framework (PiDRAM) to facilitate in-memory processing. The presentation will further explore the effects of undervolting FPGAs on the efficiency and accuracy of convolutional neural network benchmarks, including the surprising impact of temperature and humidity on fault rates. Finally, the ongoing work on utilizing the occurring faults in FPGA undervolting for random number generation (TuRaN) will be discussed, reflecting a broad exploration of cutting-edge techniques in TRNGs, DRAM technology, and FPGA efficiency.
Before we conclude our presentation, our Masters student Oguzhan Canpolat (also collaborates with SAFARI) will explain the RISC-V based processor core design efforts in the KASIRGA research group of Turkey.
Oguz Ergin is a professor and chair in the department of computer engineering, TOBB ETÜ, Ankara, Turkey. He received his BS degree in electrical engineering from Middle East Technical University in 2000 and MS, PhD degrees from State University of New York at Binghamton in 2003 and 2005 respectively. He was a senior research scientist in Intel Barcelona Research Center during 2004 and 2005. For the last 17 years he has been a faculty member in TOBB ETÜ. He was a visiting associate professor in the University of Notre Dame in 2014 and a visiting researcher in University of Edinburgh in 2015-2016. He is currently a visiting professor in ETH Zürich, as part of EFCL and SAFARI.
During this seminar I talk about the following papers briefly:
- QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips (ISCA 2021)
- DR-STRaNGe: End-to-End System Design for DRAM-based True Random Number Generators (HPCA 2022)
- DRAM Bender: An Extensible and Versatile FPGA-based Infrastructure to Easily Test State-of-the-art DRAM Chips (arXiv-2022) // This is now TCAD – OE
- PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM (ISVLSI-TACO 2022)
- An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration (DSN 2020)
- Can We Trust Undervolting in FPGA-Based Deep Learning Designs at Harsh Conditions? (IEEE MICRO Magazine 2022)
- MoRS: An Approximate Fault Modelling Framework for Reduced-Voltage SRAMs (IEEE TCAD 2022)
- TuRaN: True Random Number Generation Using Supply Voltage Underscaling in SRAMs (arXiv 2022)