Monday 1 April 2019
Siddharth Garg “Towards Secure Integrated Circuit (IC) Fabrication: A Foundational Perspective on Hardware Security”
10:30 CAB H 52
Abstract: Most semiconductor companies outsource IC fabrication to advanced external IC foundries. This is referred to as the “fabless” model. The fabless model comes at the expense of trust: Untrusted third-party foundries might overbuild and sell chips in the black market, or worse, maliciously modify the chip by inserting a “hardware Trojan”. How can a designer protect from the twin threats of IP piracy and hardware Trojans?
Much of the work in the literature has proposed heuristic defenses without formal security guarantees. I will begin the talk by demonstrating the perils of heuristic security solutions by describing a powerful class of attacks (that we call SAT attacks) against state-of-the-art IP piracy defenses. I will discuss how SAT attacks have withstood the test of time: general and provably secure defenses against these attacks are still lacking. I will then describe a well-founded approach to defending against SAT attacks using tools from cryptographic obfuscation. The second part of the talk will discuss provably secure defenses against hardware Trojans, this time by appealing to foundational work in cryptography literature on verifiable computation. I will show how we can design chips that provide proofs of their own correctness, thus mitigating against any Trojan attack that modifies the chip’s functionality. I will conclude with thoughts on the road ahead for hardware security research.
Bio: Siddharth Garg received his Ph.D. degree in Electrical and Computer Engineering from Carnegie Mellon University in 2009, an M.S. from Stanford in 2005 and a B.Tech. degree in Electrical Engineering from the Indian Institute of Technology Madras. He is an Assistant Professor at New York University in the ECE department, and prior to that, was an Assistant Professor at the University of Waterloo from 2010-2014. His general research interests are in computer engineering, and more particularly in secure, reliable and energy-efficient computing. For his work, Siddharth has received the NSF CAREER Award (2015), and paper awards at the IEEE Symposium on Security and Privacy (S&P) 2016, USENIX Security Symposium 2013, and the International Symposium on Quality in Electronic Design (ISQED) in 2009. His NDSS’15 paper will be featured in an upcoming IEEE TCAD Special Issue on “Top Picks in Hardware Security.” Siddharth also received the Angel G. Jordan Award from ECE department of Carnegie Mellon University for outstanding thesis contributions and service to the community. He serves on the technical program committee of several top conferences in the area of computer engineering and computer hardware, and has served as a reviewer for several IEEE and ACM journals.