Bachelor’s/Master’s/Semester Projects with the SAFARI Research Group

Our group works on a broad range of research domains, including all aspects of computer architecture, hardware security, bioinformatics, computer systems. More specific topic areas within these four domains include memory systems, discovery of new security vulnerabilities and defenses, emerging technologies, genome analysis, new computing and communication paradigms, acceleration of important workloads (e.g., AI, genomics, personalized medicine), computing platforms for health and medicine, fault-tolerant systems, storage systems, distributed analytics, hardware/software co-design, mobile systems, energy-efficient systems, etc. Thesis topics are available in all topics.

Please contact us if you are interested!

Below are even more specific potential thesis and semester project topics with the SAFARI Research Group. These are incomplete, so if your interest is not covered by these specific projects but falls in any of the above areas, please contact us.

 

Heterogeneous Main Memory Exploration

Explore at Imec (Leuven) and ETH how multiple memory technologies can be combined into a better, heterogeneous main memory.

In order to improve today’s computing devices like smartphones, laptops and high-performance servers, researchers must face the so-called memory wall: It is the memory within these computers that limits overall performance and energy efficiency. Aggressive technology scaling has exposed limitations of current memory and data storage technologies like SRAM, DRAM and Flash. Thus, several new emerging non-volatile memory technologies are currently being investigated to eventually satisfy the need for continuously higher storage capacity and system performance, lower energy consumption, smaller form factor, lower system costs and long data‐retention capability. Resistive RAM (RRAM), Phase Change RAM (PC-RAM) and Magneto-Resistive RAM (MRAM) are among the more mature NVM technologies. Each of these new technologies has properties of interest (e.g. non-volatility, high density, etc.), but also inherent flaws (e.g. finite write endurance, high write latency, etc.).   Read more…

 

Designing and Evaluating Energy-Efficient Main Memory

DRAM-based main memory is used in nearly all computers today, but its energy consumption is becoming a growing concern. DRAM energy utilization now accounts for as much as 40% of the total energy used by a computer.  Our goal is to design new DRAM-based memory architectures that reduce the energy consumption significantly.  This requires a principled approach, where we must measure how existing DRAM devices consume energy.  Our group has developed a sophisticated energy measurement infrastructure to collect detailed information on DRAM energy usage.  You will be involved with designing and conducting experiments to measure energy consumption using our infrastructure.  Based on the data, you will work with other researchers to identify memory operations that consume large amounts of energy, and will design new DRAM architectures that improve the efficiency of these operations.  Read more…

 

Evaluating and Enabling Processing inside Memory

Almost all data intensive workloads are bottlenecked in terms of performance and energy by the extensive data movement between processor and memory.  We are looking for an enthusiastic student who is hungry for learning and enabling a paradigm shift that can eliminate this data movement bottleneck: computation inside memory (i.e., inside where the data resides).  You will be involved in a project that aims to evaluate the benefits of executing data-intensive applications inside specialized logic in memoryand developing both mechanisms and simulatorsfor this purpose.  Read more…

 

Exploring new algorithms and hardware architectures for Genomic Sequence Alignment

Our understanding of human genomes today is affected by the ability of modern computing technology to quickly and accurately determine an individual’s entire genome. However, timely analysis of genomic data remains a challenge. One of the most fundamental computational steps in most bioinformatics analyses is genomic sequence alignment. The execution time of this step constitutes the main performance bottleneck in genomic data analysis.  In our research group, we developed several efficient hardware architectures and algorithmic solutions to tackle this problem. You will work with other researchers to design and analyze new algorithms and ideas. You will also implement and evaluate these new algorithms using real genomic data.  Read more…

 

Navigating the Main Memory Landscape with Fast and Novel Infrastructures

Memory is the major performance, energy and reliability bottleneck of all data-intensive workloads, e.g., graph processing, machine learning using large data sets, data analytics, databases, genome analysis.  The landscape of main memory is quickly changing with any technologies appearing and being proposed. This includes 3D-stacked memory designs that are capable of processing in memory, new non-volatile memory technologies that are poised to replace DRAM, and many new types of DRAM architectures. The impact of such new technologies on systems and applications need to be quickly evaluated and understood, with rigorous evaluation infrastructures.  Our group develops and openly makes available such infrastructures. A prominent example is Ramulator, which is a very flexible and fast open-source infrastructure for simulating DRAM architectures: https://github.com/CMU-SAFARI/ramulator. This infrastructure is widely used in both academia and industry (e.g., by Google, Apple, AMD, Samsung).  Your task in this project is to first understand Ramulator and then improve and extend it. Some extensions include support for the new technologies mentioned above (processing in memory, non-volatile memory, hybrid memories, new DRAM architectures). You will also evaluate the impact of such technologies on real workloads.  Read more…

 

Securing Main Memory

DRAM-based main memory is used in most computers today. Manufacturers have been optimizing DRAM capacity and bandwidth for years, but little effort has been done for designing secure memories. Our goal is to discover new security vulnerabilities in DRAM and propose new mechanisms that provide security support in DRAM. This requires characterizing DRAM under different working conditions and testing different data and address patterns. Our group has developed a DRAM testing infrastructure for memory characterization. To design new in-Memory security mechanisms, our group has developed a DRAM simulator that allows evaluating new hardware features in DRAM quickly. You will be involved with designing and conducting experiments with other researchers. The goals are: 1) discover new security vulnerabilities and identify new attack vectors that might compromise the security of the system, and 2) designing new security mechanisms that protect from these and other vulnerabilities using our infrastructure.  Read more…

 

Exploiting MLC NAND Flash Chip Error Characteristics

Multi-Level-Cell (MLC) NAND Flash Memories allow to achieve higher bit density for the same chip area compared to Single-Level-Cell (SLC) and are therefore commonly used nowadays in most commercially available SSDs. However, compared to SLC memories, they are highly susceptible to write and read interference, which can impact their reliability. To function correctly under these technological limitations, MLC SSDs use data scrambling to reduce the interference effects and Error Correction Codes (ECC) to correct the remaining bit errors. Despite these mitigations, theoretically there exist enough interference to be still able to produce arbitrary bit flips.  Read more…